Semiconductor Spacer Patterning for Sub-Lithographic Gate Pitch
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Solution Overview
Problem
As semiconductor devices continue to shrink, traditional photolithography equipment struggles to achieve the required pitch and spacing, approaching the limits of its capabilities, making it difficult to manufacture devices with increasingly smaller dimensions.
Innovation Solution
A self-aligned double patterning process is employed, where mandrels and spacers are patterned and selectively removed to achieve features at half the pitch of what is achievable with photolithography, using a carbon-rich capping layer to reduce etching damage and improve critical dimension control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithography equipment is used, then manufacturing process is simple, but manufacturing precision deteriorates due to inability to achieve required pitch and spacing
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple discrete steps: forming mandrels, depositing spacers, selective removal, and capping layer application. This multi-stage approach enables achievement of pitch and spacing below the diffraction limit of photolithography by breaking down the single-step patterning into sequential operations, thereby resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional structures by forming vertical mandrels and spacers. This dimensional transition enables pitch multiplication through the vertical stacking of layers, allowing sub-lithographic pitch achievement through self-aligned spacer formation around mandrels, thus improving manufacturing precision while managing process complexity.
2Quantity of substance
If photolithography limits are approached, then device density increases, but manufacturing precision deteriorates due to equipment limitations
Solution Approach 1:
The patent employs self-service through self-aligned spacer formation where the spacer width is determined by the mandrel dimensions and spacer deposition thickness rather than direct lithographic patterning. The mandrels automatically serve as alignment references for spacer placement, eliminating the need for additional lithographic steps to define spacer positions, thereby achieving high gate density with precise feature dimensions independent of photolithography resolution limits.
Solution Approach 2:
The patent changes the critical patterning parameter from lithographic resolution (wavelength-limited) to deposition thickness control (atom-layer precise). By transitioning from optical patterning to atomic-layer deposition for spacer formation, the critical dimension control shifts to a parameter regime where sub-nanometer precision is achievable, enabling high gate density while maintaining manufacturing precision despite approaching photolithography limits.
3Length of moving object
If pitch is reduced below photolithography capability, then device scaling continues, but manufacturing precision deteriorates due to optical diffraction limits
Solution Approach 1:
The patent introduces mandrels as intermediary structures that mediate between the lithographic patterning step and the final sub-lithographic feature formation. The mandrels serve as temporary placeholders patterned at relaxed pitch, around which spacers are formed to create the final fine-pitch features. This intermediary approach decouples the lithographic resolution requirement from the final feature pitch, enabling feature size reduction while maintaining pattern fidelity through the mandrel-spacer intermediary mechanism.
Solution Approach 2:
The patent applies preliminary action by pre-forming mandrels at a larger, lithographically achievable pitch before creating the final fine-pitch features. The mandrels are prepared in advance as templates that guide subsequent spacer formation, allowing the final feature pitch to be determined by spacer thickness rather than direct lithographic patterning. This preliminary mandrel formation enables feature size scaling below photolithography limits while preserving pattern fidelity through the pre-established mandrel template.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process allows for precise patterning and increased gate density by enabling the creation of features with reduced spacing between adjacent gates, overcoming the limitations of traditional photolithography in semiconductor manufacturing.
Implementation Method 1
depositing a carbon-rich layer over the spacers to reduce etching damage (e.g., spacer material loss) as a result of the selective removal of the mandrels and/or the spacers
Data Source
AI summary
A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.


