Spacer Patterning Mask Formation via Planarization
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Solution Overview
Problem
The existing spacer self-aligned double patterning (SADP) process in semiconductor fabrication suffers from line width roughness (LWR) issues, leading to nonuniform line width and interval, which negatively impacts device performance.
Innovation Solution
A method involving the sequential deposition of an interface layer, core film, and first hard mask on a substrate, followed by patterning, planarization, and etching of a spacer patterning layer, with precise control over separation distances and material selection to form a spacer patterning mask, including the use of silicon oxide and silicon nitride hard masks, and chemical-mechanical polishing (CMP) for planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If spacer deposition and etch process are used in the currently adopted SADP process, then the spacer patterning mask can be formed, but line width roughness (LWR) phenomena worsen, resulting in nonuniform line width and interval
Solution Approach 1:
The patent applies preliminary action by performing planarization of the spacer patterning layer before the etching process. This preliminary planarization step ensures that the spacer patterning layer has a uniform surface topology prior to etching, which prevents the LWR phenomena that would otherwise occur during the etch process. The uniform planarized surface serves as a foundation for achieving uniform line width and interval in the final spacer pattern.
2Manufacturing precision
If double patterning technology is used to continue scale-down of IC structure, then lithography precision requirements increase, but alignment precision between patterns becomes more difficult to achieve
Solution Approach 1:
The patent applies self-service through self-aligned spacer formation where the spacer patterns are automatically positioned relative to the mandrel patterns without requiring additional alignment steps. The spacer patterning layer is deposited conformally over the patterned mandrels, and subsequent planarization and etching steps naturally produce spacers that are precisely aligned to the mandrel features. This self-alignment mechanism eliminates the need for complex alignment procedures between separate lithography steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces line width roughness and improves device performance by ensuring precise alignment and uniformity of the spacer patterning mask, enhancing the precision and consistency of the semiconductor device fabrication process.
Implementation Method 1
depositing the interface layer, by using chemical vapour deposition (CVD) or furnace process
Implementation Method 2
planarizing the spacer patterning layer by using the first hard mask as a stop layer
Data Source
AI summary
The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask.