Spacer Patterning for Uniform Semiconductor Line-and-Space Arrays
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Solution Overview
Problem
Existing methods face challenges in forming uniform line widths and heights of patterns in semiconductor devices due to miniaturization, particularly in the main chip region of a substrate.
Innovation Solution
A method involving the formation of mask and spacer layers on a substrate, followed by precise etching and spin-coating processes to create uniform spacers, dummy patterns, and align key patterns, ensuring consistent line widths and heights across the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography methods are used to form patterns, then the manufacturing process is simple, but uniform line widths and heights cannot be achieved due to miniaturization
Solution Approach 1:
The manufacturing process is divided into multiple sequential stages: forming mandrels, forming spacers, forming dummy patterns, and forming align key patterns. Each stage uses a different mask layer and etching process, allowing precise control of line widths and heights at each step while maintaining overall process manageability through clear segmentation of functions
Solution Approach 2:
Mandrel structures are formed in advance before the actual pattern formation. These mandrels serve as preliminary structures that define the positions and dimensions of subsequent spacers, dummy patterns, and align key patterns, ensuring uniformity is established early in the process and maintained through later steps
2Manufacturing precision
If additional photolithography steps are added to achieve uniform patterns, then manufacturing precision improves, but productivity decreases
Solution Approach 1:
Multiple pattern formation functions (spacers, dummy patterns, align key patterns) are merged into a single integrated process flow using sequentially formed mask layers. This combination approach achieves uniform patterns without requiring separate photolithography steps for each feature, thereby maintaining high productivity while improving precision
Solution Approach 2:
The mask layers and spacer structures serve multiple functions automatically: they define pattern positions, control line widths through their own dimensions, and create alignment references. The process structures self-organize to achieve uniformity without requiring additional corrective photolithography steps, improving manufacturing efficiency
3Manufacturing precision
If conventional single-layer masking is used, then the process is fast, but pattern uniformity across the entire substrate cannot be maintained
Solution Approach 1:
The solution moves from a single-layer mask approach to a multi-layer mask architecture stacked in the vertical dimension. Each mask layer (first, second, third) operates at a different vertical level and serves specific pattern formation functions, enabling comprehensive control of pattern uniformity across the entire substrate while maintaining process speed through parallelizable operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of uniform and consistent patterns without the need for additional photolithography steps, reducing defects and ensuring uniform etching across the substrate, thereby improving manufacturing efficiency.
Implementation Method 1
spin-coating a spin-on hard mask layer on the first separation layer, wherein the spin-on hard mask layer covers the first structures, the first dummy patterns and the align key patterns
Implementation Method 2
anisotropically etching the second spacer layer to form second spacers on side walls of the first structures of the main chip region, and to form first dummy patterns and align key patterns on the side walls of the first structures of the scribe lane region
Data Source
AI summary
A method of manufacturing a semiconductor device includes: forming a mask layer, a first separation layer, a first mandrel layer, a second separation layer and a second mandrel layer on a substrate; patterning the second mandrel layer to form second mandrel patterns; forming first spacers on the second mandrel patterns; removing the second mandrel patterns; patterning the second separation layer and the first mandrel layer to form first structures; forming a second spacer layer on the first structures and the first separation layer; anisotropically etching the second spacer layer to form second spacers on the first structures, and to form first dummy patterns and align key patterns on the first structures; and spin-coating a spin-on hard mask layer on the first separation layer, wherein the spin-on hard mask layer covers the first structures, the first dummy patterns and the align key patterns.