Spacer-Assisted Via Hole Patterning to Prevent Photoresist Bridging
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Solution Overview
Problem
The scaling down of semiconductor device geometry leads to manufacturing difficulties such as hole-to-hole bridges in tri-layer photoresist patterning, which can degrade device performance and cause failures.
Innovation Solution
A spacer merge process is applied to the tri-layer photoresist to address the bridge issue between adjacent via holes, reducing the risk of via hole bridges during routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is scaled down to increase functional density, then production efficiency is improved and costs are lowered, but manufacturing precision deteriorates due to hole-to-hole bridges in patterning
Solution Approach 1:
A spacer layer is introduced as an intermediary element between the photoresist pattern and the underlying dielectric layer. This spacer acts as a mediator that prevents direct contact and potential bridging between adjacent via holes, while still allowing the patterning process to proceed. The spacer layer is deposited conformally on the photoresist and then the photoresist is removed, leaving the spacer in place to define the via hole openings without the bridging issue.
Solution Approach 2:
The patterning process is segmented into multiple steps: first forming the photoresist pattern, then depositing a spacer layer, removing the photoresist, and finally forming the via holes through the spacer. This segmentation allows each step to be optimized independently, with the spacer providing an additional structural element that prevents bridging while maintaining the benefits of scaled-down geometry.
2Manufacturing precision
If tri-layer photoresist patterning is used to achieve fine features, then manufacturing precision is improved, but hole-to-hole bridges occur causing device failures
Solution Approach 1:
The spacer layer serves as a protective intermediary that physically separates adjacent via hole openings during the patterning process. Even when the photoresist pattern achieves fine features with high precision, the spacer prevents the formation of hole-to-hole bridges by providing an additional structural barrier that maintains the integrity of adjacent features throughout subsequent processing steps.
3Area of stationary object
If via hole spacing is reduced to increase routing density, then area utilization is improved, but bridge formation risk increases
Solution Approach 1:
The photoresist material is extracted or removed after the spacer layer is deposited. This extraction leaves the spacer layer in place as a permanent structural element that continues to provide separation between via holes. By removing the photoresist while retaining the spacer, the design achieves reduced via hole spacing with maintained reliability, as the spacer prevents bridging that would otherwise occur at reduced spacings.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The spacer merge process effectively minimizes the risk of bridge formation, enhancing semiconductor device performance and reducing failure rates by ensuring accurate patterning.
Implementation Method 1
forming a spacer on the first portion of the first photoresist layer
Implementation Method 2
forming a spacer on the first portion of the first photoresist layer
Implementation Method 3
performing an etching process on the dielectric layer to form via holes
Data Source
AI summary
A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.