Spacer Width Control via Gate Feedback Trim Time
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Solution Overview
Problem
The existing methods for producing spacers in semiconductor devices face variability issues in spacer width due to the dependence on etch time, which is determined by the thickness of the dielectric layer and target spacer width, leading to inconsistent device characteristics.
Innovation Solution
An advanced process control (APC) method is introduced that considers the width of the gate and dielectric layer thickness to determine the trim time for the anisotropic dry etch process, reducing variability by using a model that accounts for the relationship between these dimensions and the spacer width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etch time is determined by dielectric layer thickness and target spacer width, then the spacer formation process is simple, but spacer width variability between lots increases
Solution Approach 1:
The patent implements feedback control by measuring the actual width of a reference structure (such as a gate or mandrel) and using this measurement to adjust the etch time for spacer formation. The system calculates a corrected etch time based on the measured dimension, ensuring that spacers are formed with the target width despite variations in previous process steps. This closed-loop approach directly addresses the variability issue while maintaining process automation.
Solution Approach 2:
The patent dynamically changes the etch time parameter based on measured process variations. Instead of using a fixed etch time determined solely by dielectric thickness and target spacer width, the system adjusts the etch time as a variable parameter that compensates for dimensional variations in underlying structures. This parameter adjustment ensures consistent spacer width across different lots despite process variability.
2Ease of operation
If fixed etch time is used based on dielectric thickness, then process control is straightforward, but spacer width precision deteriorates
Solution Approach 1:
The patent performs preliminary measurement of the reference structure width before the spacer formation etch process. This advance measurement allows the system to calculate the appropriate etch time needed to achieve the target spacer width, compensating for any deviations in the reference structure dimensions. By determining the correct etch parameters beforehand, the system ensures precise spacer width control without complicating the actual etch operation.
3Device complexity
If conventional etch process is used, then manufacturing process is simple, but variability of spacer width between lots increases
Solution Approach 1:
The patent implements feedback control by measuring the actual width of a reference structure (such as a gate or mandrel) and using this measurement to adjust the etch time for spacer formation. The system calculates a corrected etch time based on the measured dimension, ensuring that spacers are formed with the target width despite variations in previous process steps. This closed-loop approach directly addresses the variability issue while maintaining process automation.
Solution Approach 2:
The system performs self-adjustment by automatically measuring process parameters and correcting etch time without requiring manual intervention. The measurement and calculation are integrated into the process flow, allowing the manufacturing system to self-correct for variations and maintain consistent spacer width across lots, thereby improving reliability without adding significant operational complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the variability of spacer width between lots, improving the precision and consistency of semiconductor device manufacturing by incorporating feedback mechanisms to adjust trim time based on measured spacer widths.
Implementation Method 1
performing an anisotropic dry etch process, so as to form the spacers along the sidewalls of the gate
Data Source
AI summary
An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.