Spacetile Routing for IC Layer Transition
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Solution Overview
Problem
Existing electronic design routing methods face challenges in efficiently transitioning between tracked and trackless layers in integrated circuits, particularly in adhering to restrictive routing rules and varying spacing requirements, which can lead to design rule violations and increased complexity.
Innovation Solution
The method employs spacetiles to identify and subdivide routing spaces, using area probes to guide interconnect routing between layers, allowing for flexible routing between tracked and trackless layers while adhering to design rules by subdividing the routing space into spacetiles and using these as guides for area searches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a grid-based routing approach is used to satisfy restrictive routing rules, then routing rule compliance is improved, but routing flexibility and adaptability deteriorate
Solution Approach 1:
The routing space is segmented into discrete spacetiles that represent valid routing locations. Each spacetile corresponds to a specific grid position that satisfies routing rules, allowing the router to navigate through compliant paths while maintaining flexibility in route selection. The segmentation transforms continuous routing space into discrete, rule-compliant segments.
Solution Approach 2:
The patent transforms the routing problem by changing the parameter representation from continuous coordinates to discrete spacetile indices. This parameter transformation allows the router to work within restrictive rules while maintaining adaptability through tile-based pathfinding algorithms that can explore multiple valid routes.
2Manufacturing precision
If a track-based routing approach is used to satisfy alignment requirements, then design rule compliance is improved, but routing complexity and difficulty increase
Solution Approach 1:
Spacetiles serve as an intermediary representation between track-based constraints and actual routing paths. The spacetile layer mediates between the restrictive track alignment requirements and the flexible pathfinding needs, simplifying the routing process by pre-defining valid transition points between tracks.
Solution Approach 2:
The routing space is pre-processed to identify and mark valid spacetiles that satisfy alignment requirements before actual routing occurs. This preliminary action creates a ready-to-use guide map that reduces routing complexity during the actual pathfinding process, as valid locations are predetermined.
3Manufacturing precision
If restrictive routing rules are imposed to ensure manufacturability, then manufacturing precision is improved, but routing adaptability and ease of operation deteriorate
Solution Approach 1:
The spacetile-based routing system is self-adapting to restrictive rules. By encoding manufacturing constraints directly into the spacetile definitions, the routing algorithm automatically navigates compliant paths without requiring manual intervention or complex constraint checking, making the process easier to operate while maintaining high manufacturability.
4Adaptability or versatility
If gridless routing is used to maximize routing flexibility, then routing adaptability is improved, but compliance with restrictive routing rules deteriorates
Solution Approach 1:
The patent applies segmentation to transform the gridless routing space into discrete spacetiles that enforce rule compliance. This segmentation maintains routing flexibility by allowing movement between adjacent tiles while ensuring each tile position satisfies manufacturing constraints, effectively combining flexibility with compliance.
Data Source
AI summary
Various embodiments identify a routing layer of an electronic design, create spacetile(s) by performing spacetile punch(es) for the routing layer, identify an area probe from the spacetile(s), and routes the electronic design by using the one or more area probes for performing area search for routing solutions. Some embodiments identify two routing layers of an electronic design, perform spacetile punch(es) to form spacetile(s) for the routing layers, determine a via spacetile layer, identify spacetile(s) as one or more area probes based on the via spacetile layer, and routes the electronic design by using the one or more area probes for performing area search for routing solutions while transitioning between the two routing layers. One of the two routing layers may be a tracked routing layer, and the other may be a trackless routing layer. The tracked routing may be gridded or gridless.


