Spacetile Routing for Tracked and Trackless Layer Transitions

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Solution Overview

Problem

Modern integrated circuits face challenges in routing due to complex routing rules, including restrictive alignment requirements and varying spacing, which existing methods struggle to efficiently address, especially when transitioning between tracked and trackless layers.

Innovation Solution

The method involves identifying layers, performing a spacetile punch to subdivide routing space into spacetiles, and using area probes to guide routing, allowing for efficient transitions between tracked and trackless layers while adhering to design rules, including the use of soft and hard tracks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If restrictive routing rules (alignment requirements) are imposed to simplify manufacturing, then ease of manufacture is improved, but routing flexibility and adaptability deteriorate

Engineering Contradiction:
Improveease of manufactureVSAvoidrouting flexibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The routing space is segmented into discrete spacetiles with different types (tracked, trackless, via, etc.). This segmentation allows the router to handle different routing requirements in different regions, satisfying alignment rules where needed while providing flexibility where possible, thus resolving the contradiction between manufacturing ease and routing adaptability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the routing space are assigned different properties through spacetile types. Some spacetiles enforce strict alignment rules (tracked spacetiles) while others provide flexibility (trackless spacetiles). This local differentiation allows the system to maintain manufacturing ease in critical areas while preserving routing flexibility in other areas.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If complex routing rules with varying spacing are applied to meet design requirements, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvemanufacturing precisionVSAvoiddevice complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The spacetile system encodes various routing parameters (spacing requirements, alignment rules, via constraints) directly into the spacetile definitions. By changing the parameters of individual spacetiles rather than applying global complex rules, the system achieves manufacturing precision through localized parameter control, reducing overall device complexity.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If grid-based routing approach is used to simplify routing process, then ease of operation is improved, but adaptability to different spacing requirements deteriorates

Engineering Contradiction:
Improveease of operationVSAvoidadaptability to spacing
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The spacetile system serves multiple functions: it provides a grid-based structure for ease of routing operation while simultaneously accommodating different spacing requirements through varied spacetile types and configurations. This multi-functionality resolves the contradiction by making the same system adaptable to both grid-based simplicity and custom spacing needs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9075932B1Methods and systems for routing an electronic design using spacetiles
Publication Date: 2015.07.07 CADENCE DESIGN SYST INC
  • US9075932B1 patent drawing
  • US9075932B1 patent drawing
  • US9075932B1 patent drawing

AI summary

Various embodiments identify a routing layer of an electronic design, create spacetile(s) by performing spacetile punches for the muting layer, identify an area probe from the spacetiles, and routes the electronic design by using the one or more area probes for performing area search for routing solutions. Some embodiments identify two routing layers of an electronic design, perform spacetile punches to form spacetiles for the routing layers, determine a via spacetile layer, identify spacetiles as one or more area probes based on the via spacetile layer, and routes the electronic design by using the one or more area probes for performing area search for routing solutions while transitioning between the two muting layers. One of the two routing layers may be a tracked muting layer, and the other may be a trackless routing layer. The tracked muting may be gridded or gridless.