SpaceWire Data Throttling Circuit Without Clock Multiplexing
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Solution Overview
Problem
Existing methods for implementing the SpaceWire protocol on FPGAs and ASICs face difficulties in generating and distributing a 10 MHz clock signal for data throttling during link initialization, particularly due to the complexity introduced by multiplexing in the clock tree, which complicates FPGA implementation and requires off-chip clock driving.
Innovation Solution
The solution involves duplicating the full-speed data transmission to mimic a 10 MHz rate by adding storage elements and multiplexers along the data path, eliminating the need for clock multiplexing and simplifying the clock tree, while handling multiple-bit applications by replicating bits according to a throttle rate that maintains a 10 MHz output rate, even when the system clock rate is an odd multiple of 10 MHz.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multiplexer is used to select between full-speed clock and 10 MHz clock in the clock path, then data transmission at different rates is enabled, but the clock tree complexity increases and FPGA implementation becomes difficult
Solution Approach 1:
The patent removes the multiplexer from the clock path entirely, extracting the problematic element that caused complexity. Instead of multiplexing clocks, the system uses a single full-speed clock and implements rate selection through data replication in the data path, eliminating the need for clock multiplexing and its associated complexity in the clock tree
Solution Approach 2:
The patent uses data copying/replication instead of clock switching. Full-speed data is replicated multiple times to create the appearance of slower transmission. This approach allows rate adaptation without modifying the clock system, thereby avoiding clock tree complexity while maintaining versatility in transmission rates
2Reliability
If a 10 MHz clock is generated on-chip and distributed through a dedicated clock network, then SpaceWire link initialization requirement is met, but additional off-chip clock driving is required
Solution Approach 1:
The patent eliminates the need for a separate 10 MHz clock generation and distribution system by removing the requirement for dedicated clock networks and off-chip clock driving. The solution achieves SpaceWire compliance through data replication using the existing full-speed clock, thereby extracting and removing the complex clock distribution infrastructure
Solution Approach 2:
The full-speed clock serves multiple functions: it drives both the normal high-speed data transmission and, through data replication, the slowed-down 10 MHz transmission during link initialization. This multi-functionality eliminates the need for separate clock systems while maintaining SpaceWire protocol compliance
3Productivity
If data is transmitted at full speed during normal operation, then transmission efficiency is maximized, but link initialization requires slowed transmission at 10 MHz
Solution Approach 1:
The patent implements dynamic transmission rate adaptation where the system operates at full speed during normal production phases and dynamically switches to slowed transmission through data replication during link initialization. This dynamic approach allows the system to optimize for productivity during normal operation while adapting to initialization requirements when needed
Data Source
AI summary
A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bit0 is transmitted for half the time and bit1 is transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a “split cycle” including one bit0 and one bit1.