SPAD Array Readout Using Distributed OR Tree

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Solution Overview

Problem

Existing SPAD arrays face limitations in size and number due to routing congestion and mismatched signal path lengths, which affect the accuracy and scalability of photon detection in time-of-flight imaging applications.

Innovation Solution

The implementation of a distributed OR tree with pulse shaping circuits and in-pixel memory within an array of SPAD pixels, where each pixel has a quench circuit and a pulse shaper, and OR logic elements are positioned to ensure equal signal path lengths, reducing congestion and delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional readout circuitry and signal paths are used in SPAD arrays, then the array can perform photon detection, but the overall size and number of SPADs are limited due to routing congestion

Engineering Contradiction:
Improvenumber of SPADsVSAvoidrouting congestion
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The readout circuitry is segmented and distributed across multiple layers. OR logic elements are placed between columns of SPADs in one layer, while additional OR logic elements are placed in a second layer, creating a distributed hierarchical readout structure that reduces routing congestion in any single layer

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes a three-dimensional stacked architecture where readout circuitry is distributed across multiple vertical layers. This adds a vertical dimension to the readout path, allowing signals to travel through multiple layers via through-silicon vias (TSVs) rather than being confined to a single planar layer, thereby reducing routing congestion

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If readout circuitry is added to enable SPAD array operation, then photon detection capability is achieved, but the overall array size is constrained

Engineering Contradiction:
Improvearray sizeVSAvoidarray area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

By distributing readout circuitry across multiple vertical layers and using TSVs for inter-layer communication, the patent reduces the horizontal area required for routing. This allows more SPADs to be packed into a given footprint area while maintaining full readout capability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple functional elements (SPADs, quench circuits, pulse shaping circuits, memory cells, and OR logic elements) are integrated into compact pixel structures. The distributed OR tree architecture merges readout functions across multiple layers, reducing the total area required compared to traditional planar implementations

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If signal paths are extended to connect all SPADs to readout circuitry, then complete readout is achieved, but signal propagation delays vary across the array

Engineering Contradiction:
Improvereadout completenessVSAvoidsignal path length matching
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The signal path is segmented into standardized sections: SPAD to quench circuit, quench circuit to pulse shaping circuit, pulse shaping circuit to OR logic element, and inter-layer TSV connections. Each segment has controlled length and delay characteristics, allowing overall path matching across the array

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The distributed OR tree architecture is designed so that all signal paths from any SPAD to the final readout output have equal total length and therefore equal propagation delay. This is achieved by carefully balancing the number and arrangement of TSVs and logic elements along each path, creating equipotential signal arrival times across the array

Inventive Principle:
Principle #12Equipotentiality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the accuracy and scalability of SPAD arrays by minimizing routing congestion, reducing signal propagation delays, and allowing for a larger number of pixels per unit area without introducing additional delays, thus improving the overall performance in time-of-flight imaging.

Implementation Method 1

Single Photon Avalanche Diodes (SPADs) are semiconductor photon detection devices based on a p-n junction reverse-biased at a voltage that exceeds a breakdown voltage VB of the junction. At this bias, the electric field is so high that a single charge carrier injected into the depletion layer can trigger a self-sustaining avalanche.

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Implementation Method 2

The current continues until the avalanche is quenched by lowering the bias voltage until the current ceases. In order to detect another photon, the bias voltage must be raised again above breakdown.

Methodology Applied
Scientific EffectElectrical breakdown and quenching: Avalanche Breakdown

Data Source

PatentUS10332930B2Single photon avalanche diode (SPAD) array including distributed or tree for readout
Publication Date: 2019.06.25 STMICROELECTRONICS (RES & DEV) LTD
  • US10332930B2 patent drawing
  • US10332930B2 patent drawing
  • US10332930B2 patent drawing

AI summary

A device includes an array of single photon avalanche diodes (SPADs) and a plurality of pulse shapers. Each of the SPADs are electrically coupled to a respective SPAD quench circuit. Each of the pulse shapers have an input electrically coupled to an output of a respective SPAD quench circuit.