SPAD Output Combining Circuit for Photon Pile-Up Reduction
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Solution Overview
Problem
Time-of-flight ranging devices based on single-photon avalanche diodes (SPADs) face challenges in wide field-of-view scanning, varying target reflectivity, and harsh ambient conditions, particularly due to photon pile-up distortion and saturation issues in existing combining networks.
Innovation Solution
A circuit and method utilizing a combining network with synchronous sampling circuits and a summation circuit, including an adder tree, flip-flops, and edge detection devices, to generate a binary output value by counting pulses or edges, effectively addressing photon pile-up distortion and improving detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional combining network is used to aggregate SPAD outputs, then the circuit complexity is reduced, but photon pile-up distortion and saturation occur at high ambient light levels
Solution Approach 1:
The patent divides the SPAD array outputs into multiple groups, with each group processed by a dedicated synchronous sampling circuit. This segmentation allows parallel processing of multiple SPAD outputs without causing photon pile-up distortion, as each sampling circuit independently captures events from its assigned SPADs at precise clock edges.
Solution Approach 2:
The patent employs periodic clock signals to synchronize the sampling of SPAD outputs. By sampling at regular intervals aligned with the clock period, the system captures photon events periodically, preventing saturation and maintaining linearity even at high ambient light levels while avoiding photon pile-up distortion.
2Measurement precision
If synchronous sampling circuits are used to reduce photon pile-up distortion, then detection accuracy improves, but the device complexity increases
Solution Approach 1:
The patent merges multiple SPAD outputs that are sampled simultaneously by the same synchronous sampling circuit into a single combined output signal. This merging reduces the number of separate processing paths needed, thereby decreasing overall circuit complexity while maintaining the accuracy benefits of synchronous sampling.
Solution Approach 2:
The synchronous sampling circuits are designed as universal modules that can process multiple SPAD outputs. Each sampling circuit serves multiple SPADs within its group, making the circuitry multi-functional and reducing the total number of sampling circuits required compared to one-to-one mapping.
3Productivity
If the sampling clock period is reduced to capture more events, then the detection rate increases, but the risk of missing events due to pulse duration increases
Solution Approach 1:
The patent optimizes the relationship between clock period and pulse duration as key parameters. By carefully selecting the clock period to be less than half the pulse duration, the system achieves the maximum detection rate while ensuring that each pulse is properly captured without being missed, thus maintaining reliable event detection.
Data Source
AI summary
A combining network for an array of SPAD devices includes: synchronous sampling circuits, wherein each synchronous sampling circuit is coupled to an output of a corresponding SPAD device and is configured to generate a pulse or an edge each time an event is detected; and a summation circuit coupled to an output of each of the synchronous sampling circuits and configured to count a number of pulses or edges to generate a binary output value.