SPAD Imaging Sensor Stacked Chip Fill Factor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional single photon avalanche diode (SPAD) imaging sensors face challenges in achieving optimal detection efficiency, spectral response, and timing resolution due to limitations in standard CMOS processes, which hinder full depletion operation and result in reduced fill factor and poor performance in high-resolution, low-power applications.
Innovation Solution
A stacked chip configuration with fully depleted SPAD regions on a custom CMOS processor chip, where SPADs are back side illuminated and separated from CMOS circuitry, allowing for high NIR sensitivity, improved timing resolution, and flexible circuit connections, enabling a high fill factor and small pitch photon timing sensors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If SPADs are arranged in the same plane as MOSFETs in standard CMOS process, then integration is achieved, but fill factor is reduced
Solution Approach 1:
The patent transitions from a planar 2D arrangement to a 3D stacked configuration by separating SPADs and MOSFETs onto different chips that are vertically bonded together. This dimensional change allows both components to occupy their optimal spaces without planar interference, resolving the fill factor reduction issue while maintaining integration.
Solution Approach 2:
The patent divides the integrated sensor into two separate functional modules: a SPAD chip for photon detection and a CMOS chip for signal processing. This segmentation allows each component to be optimized independently and bonded together, eliminating the need for co-planar arrangement and restoring high fill factor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high sensitivity, excellent timing resolution, and high fill factor in SPAD imaging sensors, overcoming the limitations of conventional designs by allowing full depletion and separate optimization of SPAD and CMOS components, resulting in enhanced performance in both near-infrared sensitivity and blue performance.
Implementation Method 1
The SPAD regions have a p-n junction that is reverse biased above the breakdown voltage such that a single photo-generated carrier can trigger an avalanche multiplication process that causes current at the output of the photon detection cell to reach its final value quickly
Implementation Method 2
A SPAD (also referred to as a Geiger-mode avalanche photodiode (GM-APD)) is a solid-state photodetector capable of detecting a low intensity signal, such as low as a single photon
Data Source
AI summary
An imaging sensor system includes a single photon avalanche diode (SPAD) imaging array including N pixels formed in a first semiconductor layer of a first wafer. Substantially an entire thickness of the first semiconductor layer of each pixel is fully depleted such that a multiplication region included in each pixel near a front side is configured to be illuminated with photons through a back side and through the substantially entire thickness of the fully depleted first semiconductor layer. Deep n type isolation regions are disposed in the first semiconductor layer between the pixels to isolate the pixels. N digital counters are formed in a second semiconductor layer of a second wafer that is bonded to the first wafer. Each of the N digital counters is coupled to the SPAD imaging array and coupled to count output pulses generated by a respective one of the pixels.