Spare Bump Routing for Semiconductor Stacked Package Yield
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Solution Overview
Problem
The semiconductor industry faces challenges in yield reduction due to failed bumps in stacked packages, leading to discarding of semiconductor chips and increased costs, as existing technologies require pre-stacking bump testing and do not efficiently utilize spare bumps for signal routing.
Innovation Solution
Incorporating spare bumps and through electrodes in semiconductor chips that can be selectively routed to replace failed bumps, allowing for the establishment of vertical input/output lines through selective signal routing, thereby minimizing chip discard and increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-stacking bump testing is performed and chips with failed bumps are discarded, then mounting reliability is improved, but yield is reduced and costs increase
Solution Approach 1:
The patent performs bump testing before stacking, but instead of discarding chips with failed bumps, it pre-configures spare bumps and establishes alternative signal paths in advance. This preliminary preparation allows the chip to be rescued and reused after failure detection, thereby maintaining high mounting reliability while significantly improving yield by preventing chip discard.
Solution Approach 2:
The patent changes the state of bump connectivity by introducing selectable signal paths that can dynamically switch between normal bumps and spare bumps. Through control signals, the electrical connection parameters are changed to route signals through alternative paths when failures occur, enabling the system to adapt to failure conditions without discarding the chip.
2Productivity
If spare bumps are added to replace failed bumps, then yield is improved, but device complexity increases
Solution Approach 1:
The spare bumps are designed to serve multiple purposes: they remain inactive during normal operation and only activate when a bump failure occurs. This multi-functionality allows the same spare bump structure to handle multiple potential failure points, improving yield without proportionally increasing complexity. The control mechanism selectively activates only the necessary spare paths.
Solution Approach 2:
The patent introduces control signals and switching mechanisms as intermediaries between the bumps and the substrate. These intermediaries manage the complexity by providing a systematic way to route signals through either normal or spare bumps based on failure conditions, rather than creating direct complex connections between all possible bump combinations.
3Productivity
If selective signal routing is implemented to establish alternative paths, then chip reuse is enabled and yield increases, but manufacturing complexity increases
Solution Approach 1:
The alternative signal paths are pre-configured during the manufacturing process before the chip is stacked. The spare bumps and their corresponding signal routes are prepared in advance with control logic already in place. This preliminary configuration simplifies manufacturing by avoiding the need for complex post-failure modifications or rework, allowing selective routing to be implemented through standard manufacturing processes.
4Reliability
If spare components are added to the semiconductor chip, then reliability is improved through fault tolerance, but chip area increases
Solution Approach 1:
The spare bumps are positioned in specific locations on the chip substrate where they can serve multiple potential failure points. Rather than distributing spare components uniformly across the entire chip area, the patent places them strategically to provide fault tolerance for critical signal paths while minimizing the total area occupied by spare components.
Data Source
AI summary
A stacked package including: a semiconductor substrate, a circuit layer formed over the semiconductor substrate, a bump formed over the circuit layer, a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump, a through electrode configuring to pass through the semiconductor substrate on a same line as the bump and electrically coupled the bump or the spare bump in response to a selection signal, and a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically coupled with the bump or the spare bump in response to a selection signal. When a bump has failed, a vertical input/output line of the semiconductor chips is established by a spare bump corresponding to the failed bump through the selective signal routing.