Spare Cell Gate Biasing for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing density of cells in integrated circuits leads to higher power consumption, particularly from spare cells, which contributes to overall leakage current and reduces efficiency.
Innovation Solution
The integration circuit design includes a configuration where the gates of p-type channel field effect transistors in spare cells are connected to a positive voltage terminal, and the gates of n-type channel field effect transistors are connected to a negative voltage terminal, effectively turning off spare cells to reduce leakage current and power consumption, while maintaining design flexibility for engineering change orders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the density of spare cells is increased to improve interconnectivity and functionality choices, then the adaptability of the integrated circuit is improved, but the power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating the electrical state of spare cell gates from regular cells. Spare cell gates are connected to voltage terminals that maintain them in a non-conducting state, while regular cells operate normally. This localized differentiation allows spare cells to remain available for engineering change orders without contributing to overall power consumption.
Solution Approach 2:
The patent changes the electrical parameter (voltage potential) of spare cell gates by connecting them to voltage terminals. This parameter change transitions the spare cells from an active conducting state to an inactive non-conducting state, reducing leakage current while preserving their structural availability for future modifications.
2Productivity
If the density of cells is increased to improve functionality, then the productivity of the integrated circuit is improved, but the power consumption increases dramatically
Solution Approach 1:
The patent applies local quality by creating distinct electrical zones within the integrated circuit. Regular cells operate with normal gate voltages for full functionality, while spare cells are placed in a different electrical state by connecting their gates to voltage terminals, making them non-conducting. This allows high cell density without proportional power consumption increases.
Solution Approach 2:
The patent segments the cell population into two functional groups: regular cells that are active and spare cells that are inactive. This segmentation is achieved through different gate connection arrangements, where spare cell gates are connected to voltage terminals while regular cell gates are connected to functional logic. This segmentation allows the circuit to maintain high density while controlling overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces gate leakage and subthreshold leakage, resulting in lower overall power consumption without compromising the ability to modify the functional logic of the integrated circuit during engineering change orders.
Implementation Method 1
each transistor has a gate... connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells to the first voltage terminal; and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells to the second voltage terminal
Data Source
AI summary
The disclosure relates to an integrated circuit comprising: a first voltage terminal; a second voltage terminal; and a plurality of logic cells, comprising one or more field effect transistors having a p-type channel and one or more field effect transistors having an n-type channel. The plurality of logic cells comprises a regular subset of cells and a spare subset of cells. Electrical connectors are arranged to: connect the gates of the regular subset of cells in order to provide a functional logic arrangement; connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells to the first voltage terminal; and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells to the second voltage terminal.