Spare Cell Wiring Bypass for Semiconductor Logic Modification
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Solution Overview
Problem
Current methods for logic modification in semiconductor integrated circuit devices require significant changes to photomasks and processes, leading to increased costs and longer turnaround times, especially when adding complex logic circuits, making them impractical for current manufacturing conditions.
Innovation Solution
A semiconductor integrated circuit device with a spare cell region that includes P-channel and N-channel transistor regions, gate electrodes, a main wire layer, and bypass wires, allowing for connections at multiple points without needing new contact holes, enabling easy logic modification and addition of complex circuits without altering other wire layers or contact holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If new transistors are added for logic modification, then the logic circuit can be corrected or modified, but process correction is required as far back as the diffusion process and almost all photomasks must be changed, leading to marked increase in manufacturing cost and turnaround time
Solution Approach 1:
The patent applies preliminary action by providing spare transistors and wiring patterns in advance during the initial device fabrication. The spare cell region is pre-configured with transistors, contact holes, and wiring patterns that can be activated later through simple photomask changes, avoiding the need for extensive process corrections and new photomask fabrication when logic modification is needed.
Solution Approach 2:
The patent segments the device into a main circuit region and a separate spare cell region. The spare cell region contains pre-fabricated transistors and wiring patterns that can be independently activated or deactivated. This segmentation allows logic modification to be achieved by simply changing which regions are activated, without affecting the main circuit fabrication process.
2Device complexity
If wiring patterns are independently provided above CMOS basic cells to mitigate wiring density, then wiring complexity is reduced, but process correction is still required as far back as the contact hole forming process, resulting in increased cost and turnaround time
Solution Approach 1:
The patent provides wiring patterns and contact holes in advance as part of the spare cell region during initial fabrication. Multiple wiring patterns are pre-formed at different locations, and the desired wiring configuration is achieved by selectively activating these pre-formed patterns through photomask changes, eliminating the need for process corrections to contact hole formation.
Solution Approach 2:
The patent utilizes multiple layers and dimensions in the spare cell region, with wiring patterns provided at different heights and locations. This multi-dimensional arrangement allows complex wiring to be achieved by selecting and connecting appropriate pre-formed patterns, reducing wiring density in any single layer while avoiding process corrections.
3Adaptability or versatility
If existing logic modification methods are used, then simple modifications may be achieved, but it is impossible or very difficult to add complex logic circuits
Solution Approach 1:
The patent provides a comprehensive spare cell region with pre-fabricated transistors, multiple wiring patterns, and contact holes configured to support complex logic circuits. The pre-formed structures include various wiring patterns that can be combined to create complex logic functions, and the spare transistors can be activated through simple photomask changes to implement complex circuit modifications.
Solution Approach 2:
The spare cell region is designed with universal components that can be configured to implement various logic functions. Multiple wiring patterns and spare transistors are provided in a way that allows the same physical structures to serve multiple logical purposes, enabling the addition of complex logic circuits through reconfiguration rather than physical modification.
Data Source
AI summary
A semiconductor integrated circuit device includes a main region on which a main circuit is formed and a spare cell region for logic modification of the circuit formed on the main region. The spare cell region includes a P-channel transistor region, an N-channel transistor region, a plurality of gate electrodes provided above the P-channel transistor region and the N-channel transistor region, a main wire layer that is a different layer from the gate electrodes, and a plurality of bypass wires that are formed at a different layer from the main wire layer. Each of the plurality of bypass wires has a structure that can be connected to the main wire layer at more than one point through contact holes formed in a dielectric layer intervening between the main wire layer and the bypass wires.