Spare Latch Placement Quality Determination in IC Floor Plans
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuit design tools lack an effective mechanism to determine and assess the quality of spare latch placement in floor plans, which can lead to undesirable locations that reduce their usefulness in implementing engineering change orders (ECOs), especially in larger or more complex designs.
Innovation Solution
A method and system for determining spare latch placement quality (SLPQ) using a defined metric that considers multiple physical and timing attributes, such as static timing slack, wiring distance, and clock domain, allowing for the generation of reports that inform hardware designers and enable optimization of spare latch placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If spare latches are inserted into random logic macros and processed through standard design methodology, then the design process is simplified and follows typical flow, but the final physical location of spare latches may be in undesirable locations that reduce their helpfulness for ECOs
Solution Approach 1:
The patent applies preliminary action by calculating and determining the quality of spare latch placement early in the design process, before final placement decisions are made. The SLPQ metric is computed during floorplanning stages to predict future usefulness, allowing designers to adjust placement before it's too late, thus preventing the problem rather than correcting it afterward.
Solution Approach 2:
The patent implements feedback by generating reports that communicate the quality of spare latch placement back to designers. These reports provide actionable information about placement quality based on multiple factors including timing, wiring distance, and density, enabling designers to make informed decisions about whether to accept or adjust the current placement.
2Productivity
If floor planning tools temporarily assign unplaced gates like spare latches in the lower left corner, then placement is quick and easy to implement, but spare latches may end up in locations that are impractically far from the logic that needs them
Solution Approach 1:
The patent replaces the simple geometric heuristic (lower-left corner assignment) with a comprehensive metric-based evaluation system. Instead of using a fixed mechanical rule for placement, the system uses the SLPQ metric that considers timing, wiring distance, and density factors to evaluate placement quality, allowing for more intelligent and context-aware placement decisions.
Solution Approach 2:
The patent changes the parameters used to evaluate placement from a single geometric parameter (position in lower-left corner) to multiple parameters including timing slack, wiring distance to non-spare latches, and local density. This multi-parameter approach allows for more nuanced evaluation and optimization of spare latch placement.
3Ease of manufacture
If a simple visualization method is used to show the location of all spare latches, then the implementation is straightforward and quick, but it does not provide enough information for hardware designers to make informed decisions about placement quality
Solution Approach 1:
The patent applies segmentation by breaking down the complex evaluation of placement quality into multiple distinct factors or segments: timing slack, wiring distance to non-spare latches, and local density. Each factor is evaluated separately and then combined into the overall SLPQ metric, providing a comprehensive view that is more informative than a single visualization.
Solution Approach 2:
The patent adds another dimension to the evaluation by incorporating multiple factors beyond simple spatial location. Instead of just showing where spares are located (2D position), the system evaluates and reports on multiple dimensions including timing characteristics, wiring distances, and density metrics, providing a multi-dimensional assessment of placement quality.
Data Source
AI summary
A method, system and computer program product are provided for implementing spare latch placement quality (SLPQ) determination in a floor plan design of an integrated circuit chip. A spare latch placement quality (SLPQ) metric data function is defined and compared to a spare latch placement input with a series of calculations performed. The spare latch placement quality (SLPQ) determination is made based upon the compared SLPQ metric data function and the spare latch placement input. Then associated reports including textual and visual reports are generated responsive to the SLPQ determination. In addition, a new spare latch placement can be constructed with an algorithm responsive to the SLPQ determination.