Spare Local Wordline Circuitry for Defective Memory Cell Repair
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Solution Overview
Problem
As memory cell density increases, managing defective wordlines in semiconductor memory devices becomes complex, necessitating an innovative mechanism for effective repair and replacement.
Innovation Solution
A method and circuitry are introduced that utilize spare local wordlines to repair or replace defective regular local wordlines by generating match signals and assignable bits through address comparison, enabling flexible replacement using spare wordline decoders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased, then memory capacity is improved, but management complexity of defective wordlines increases
Solution Approach 1:
The patent divides the wordline management system into regular local wordlines and spare local wordlines, with dedicated decoders for each type. The address space is segmented into regular address bits and assignable bits, allowing independent management of defective and non-defective wordlines. This segmentation reduces the complexity of managing defective wordlines in high-density memory by creating modular, independently controllable units.
2Reliability
If spare local wordlines are used to repair defective regular local wordlines, then reliability is improved, but address bit assignment complexity increases
Solution Approach 1:
The patent implements dynamic address bit assignment where assignable bits are selectively used based on whether a wordline is defective or not. During normal operation, regular address bits are used for non-defective wordlines. When a defective wordline is detected, the system dynamically switches to using assignable bits for addressing the spare wordline. This dynamic adaptation simplifies the overall system by providing flexibility rather than requiring complex static reconfiguration.
Solution Approach 2:
The patent introduces an intermediary mechanism (the assignable bits and spare control logic) that mediates between the input address and the wordline activation. This intermediary layer translates regular addresses to appropriate spare wordline addresses when defects are present, without requiring complex changes to the overall addressing scheme. The intermediary absorbs the complexity of defect management while maintaining simple external interfaces.
3Reliability
If conventional defective wordline replacement is implemented, then functionality is maintained, but flexibility of repair mechanism is reduced
Solution Approach 1:
The patent creates a universal spare wordline system where spare local wordlines can replace any defective regular local wordline within their bank, regardless of the specific address. The assignable bits enable the same spare wordline to serve multiple different address patterns. This multi-functional capability significantly increases the flexibility of the repair mechanism compared to conventional one-to-one replacement schemes.
Data Source
AI summary
A method for handling defective regular local wordlines in a memory module is provided. The method includes: providing one or more sets of spare local wordlines; utilizing a spare control logic to generate a plurality of match signals by comparing an input address with a plurality of fail addresses; utilizing the spare control logic to generate at least one assignable bit according to the plurality of match signals; utilizing a local wordline pre-decoder to generate a local wordline activation signal according to one of at least one bit of the input address and the at least one assignable bit; and in accordance with the input address and the local wordline activation signal, utilizing the one or more spare wordline decoders to activate one spare local wordline from the one or more sets of spare local wordlines for repairing/replacing a defective regular local wordline.