Dynamic Cache Tuning for Spark DAG Memory Contention

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Solution Overview

Problem

In-memory Spark platforms face performance degradation and low memory efficiency due to suboptimal memory management, particularly because the current Least Recently Used (LRU) policy is oblivious to Directed Acyclic Graph (DAG) scheduling, leading to inefficient caching of intermediate data.

Innovation Solution

Implement dynamic memory tuning by obtaining memory usage statistics from worker nodes to adjust the size of distributed dataset caches, increasing cache size when tasks use too little memory and decreasing it when contention occurs, thereby optimizing cache management based on DAG information and task dependencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If traditional LRU cache management policy is used, then implementation is simple, but memory utilization efficiency is low and performance degrades

Engineering Contradiction:
Improveease of implementationVSAvoidmemory utilization efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent transitions from static LRU cache management to dynamic DAG-aware cache management. The system dynamically adjusts cache retention decisions based on real-time DAG scheduling information, task dependencies, and data access patterns, allowing the cache management strategy to adapt to changing workload requirements and improve memory utilization efficiency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback mechanisms where the cache manager continuously monitors DAG scheduling status, task execution progress, and data access patterns. This feedback information is used to dynamically adjust cache retention decisions, creating a closed-loop control system that optimizes memory utilization based on actual system state

Inventive Principle:
Principle #23Feedback

2Productivity

If RDD data is cached in memory to avoid re-computation, then computation performance is improved, but memory becomes a scarce resource

Engineering Contradiction:
Improvecomputation performanceVSAvoidmemory availability
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent changes the parameter of cache management from fixed LRU eviction to dynamic retention decisions based on DAG scheduling parameters. By considering task dependencies, scheduling status, and data access patterns, the system optimizes which RDD data to retain in memory versus evict to disk, improving computation performance while managing memory resources more effectively

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent performs preliminary actions by pre-fetching and caching RDD data that is likely to be needed based on DAG scheduling information and task dependencies. This proactive caching strategy ensures that required data is available in memory before computation tasks execute, improving computation performance while reducing unnecessary memory consumption

Inventive Principle:
Principle #10Preliminary action

3Speed

If cache size is increased to reduce I/O operations, then computation speed improves, but I/O bottlenecks occur when multiple tasks contend for memory

Engineering Contradiction:
Improvecomputation speedVSAvoidI/O bottlenecks
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by providing differentiated cache management for different RDD data based on their specific DAG scheduling context, task dependencies, and access patterns. Instead of uniform cache management, the system tailors retention decisions to local requirements of each data set, optimizing computation speed while minimizing I/O bottlenecks through targeted caching strategies

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10204175B2Dynamic memory tuning for in-memory data analytic platforms
Publication Date: 2019.02.12 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10204175B2 patent drawing
  • US10204175B2 patent drawing
  • US10204175B2 patent drawing

AI summary

At a cache manager of a directed acyclic graph-based data analytic platform, memory usage statistics are obtained from each of a plurality of monitor components on a plurality of worker nodes. The worker nodes have a plurality of tasks executing thereon, and each of the tasks has at least one distributed dataset associated therewith. Each of the worker nodes has a distributed dataset cache. At least one of the following is carried out: increasing a size of a given one of the distributed dataset caches if the memory usage statistics indicate that corresponding ones of the tasks are using too little memory; and decreasing a size of another given one of the distributed dataset caches if the memory usage statistics indicate contention between corresponding ones of the tasks and a corresponding one of the distributed datasets.