Spark Plug Chip Welding Thermal Stress Reduction
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Solution Overview
Problem
Spark plug electrodes with metal chips experience thermal stress issues due to differing thermal expansion coefficients, leading to premature peeling, deformation, or breakage, as oxide scales form and chips are detached from electrodes.
Innovation Solution
A spark plug design with a chip having a thermal expansion coefficient smaller than the electrode, featuring a significant noble metal content difference and an intermediate layer with strategically placed holes to reduce thermal stress and enhance weldability, preventing peeling and deformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the chip is welded very strongly to the electrode to suppress oxide scale formation, then weldability is improved, but the chip experiences thermal expansion stress and may deform or break
Solution Approach 1:
The patent introduces a porous intermediate layer between the chip and electrode, containing holes with a length-to-boundary ratio of 0.05 to 0.5. This porous structure absorbs thermal expansion stress, preventing chip deformation and breakage while maintaining strong weldability and suppressing oxide scale formation.
2Strength
If the thermal expansion coefficient difference between chip and electrode is large, then wear resistance is improved, but thermal stress increases causing peeling and detachment
Solution Approach 1:
The patent introduces an intermediate layer as a mediator between the chip and electrode. This intermediate layer with controlled porosity buffers the thermal expansion coefficient difference, preventing direct stress transmission that would cause peeling and detachment, while maintaining the wear resistance benefits of the high-noble metal chip.
3Reliability
If the noble metal content difference between chip and electrode is increased, then weldability is improved, but thermal expansion stress concentration increases
Solution Approach 1:
The porous intermediate layer with specifically controlled hole distribution (0.05 ≤ N/L ≤ 0.5) disperses thermal stress concentration that would otherwise occur at the chip-electrode interface due to noble metal content differences, while maintaining the weldability benefits of the composition gradient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces thermal stress and oxide scale formation, improving chip weldability and preventing deformation or breakage, while maintaining excellent wear resistance and ignitability.
Implementation Method 1
the thermal expansion coefficient of the chip is smaller than the thermal expansion coefficient of the electrode to which the chip is welded. Thus, at high temperature, the difference in thermal stress between the chips and the electrodes becomes relatively large.
Implementation Method 2
the noble metal component contained in the chip or the electrode can be caused to sufficiently diffuse when in use (at high temperature)
Implementation Method 3
oxide scales are rapidly formed between the chips and the electrodes as a thermal cycle is repeated
Data Source
AI summary
Peeling (detachment) and deformation and the like of a chip is effectively prevented. A spark plug 1 is provided with: a central electrode 5; a ground electrode 27 forming a spark discharge gap 33 with the center electrode 5; and a chip 31(32) welded to at least one of the electrodes 5 and 27. The chip 31(32) has a thermal expansion coefficient smaller than a thermal expansion coefficient of the electrode 27(5) to which the chip is welded, and the difference between the content A (mass%) of a noble metal component in the chip 31 (32) and the content B (mass%) of a noble metal component in the electrode 27(5) (A - B) is 50 mass% or more. In an intermediate layer 34(35) between the chip 31(32) and the electrode 27(5), holes 38(39) are present. When the length of a boundary between the chip 31(32) and the intermediate layer 34(35) is L (mm), and the length of the holes 38(39) in a direction along the boundary of the chip 31 (32) and the intermediate layer 34(35) is N (mm), 0.1 ≤ N/L ≤ 0.4.