Sparse Access Buffer for Selective Cache Line Sector Handling
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Solution Overview
Problem
Modern processors face inefficiencies in handling memory accesses for data with non-locality, leading to cache pollution and bandwidth waste due to full cache line fetching, which is not optimized for pseudo-random or irregular access patterns common in sparse data processing workloads like graph analytics.
Innovation Solution
Implementing no-locality (NL) load instructions that allow for fine-grained memory access, bypassing the cache hierarchy, and using a sparse access buffer to dynamically detect locality potential, enabling sub-cache line data access and storage, thereby optimizing memory access for data with insufficient spatial and temporal locality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If full cache lines are fetched from memory for sparse data processing workloads, then memory access capabilities are provided, but cache pollution and bandwidth waste occur
Solution Approach 1:
The patent segments the cache line into multiple sectors, allowing selective storage and access of only the relevant portions of memory data. This segmentation enables the system to avoid bringing in unnecessary data into the cache, thereby reducing cache pollution while still providing fine-grained memory access capabilities for sparse data processing workloads.
Solution Approach 2:
The patent implements different access and storage characteristics for different sectors of the cache line based on their locality properties. Sectors with high locality are stored in cache for future reuse, while sectors with low locality are accessed directly from memory without cache storage. This local quality differentiation optimizes bandwidth utilization by avoiding redundant memory transfers for non-local data.
2Adaptability or versatility
If sub-cache line memory accesses are implemented, then fine-grain memory access capabilities are provided, but cache design complexity increases
Solution Approach 1:
The cache line is divided into multiple sectors that can be independently accessed and managed. This segmentation allows the cache to handle sub-cache line memory accesses by selectively accessing individual sectors without requiring a complete redesign of the cache architecture. The sector-based approach provides fine-grained access capability while maintaining relatively simple cache control logic.
Solution Approach 2:
The patent implements partial cache line storage by allowing the cache to store only the necessary sectors of a cache line rather than the entire line. This partial action approach provides fine-grained memory access capability by enabling selective sector access while avoiding the complexity of implementing complete sub-cache line granularity throughout the entire cache hierarchy.
3Speed
If full cache lines are fetched for pseudo-random access patterns, then memory access is enabled, but external memory bandwidth is wasted
Solution Approach 1:
The patent segments memory access into sector-level operations, allowing the system to access only the specific sectors needed for pseudo-random access patterns rather than fetching entire cache lines. This segmentation maintains memory access speed by providing direct sector access while eliminating bandwidth waste by avoiding transfer of unnecessary data sectors.
Solution Approach 2:
The patent applies different access strategies to different sectors based on their locality characteristics. For pseudo-random access patterns, sectors are accessed based on their specific needs rather than bringing in entire cache lines. This local quality approach optimizes memory bandwidth utilization by transferring only the necessary data portions while maintaining access speed through direct memory interface support.
Data Source
AI summary
In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.