Sparse Circuit Matrix Partitioning for Parallel Linear Simulation
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Solution Overview
Problem
Existing methods for large-scale circuit simulation face inefficiencies due to the inability to control the number and sizes of matrix blocks during sparse matrix factorization, leading to lower efficiency in circuit simulation.
Innovation Solution
A method and system for large-scale linear circuit simulation that constructs ordinary differential equations, converts them into sparse systems using Euler iteration, performs column reordering to ensure diagonal elements are non-zero, and utilizes graph partitioning to distribute non-zero elements along the diagonal and borders, employing multiple compute nodes to solve local Schur complements and sum them up to obtain a global Schur complement, allowing parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If matrix reordering methods are used to decompose sparse matrices, then the simulation can proceed, but the number and sizes of matrix blocks cannot be controlled, leading to lower efficiency
Solution Approach 1:
The patent divides the large-scale sparse matrix into multiple smaller sub-matrices through graph partitioning, creating a bordered-block diagonal structure. This segmentation allows each sub-matrix to be processed independently and in parallel, improving simulation efficiency while maintaining controllability over the number and size of matrix blocks.
Solution Approach 2:
The patent performs preliminary graph partitioning and matrix reordering before the actual simulation process. By pre-organizing the matrix into a bordered-block diagonal form with controlled sub-matrix sizes, the system prepares the computational structure in advance, enabling efficient parallel processing during simulation without requiring dynamic control during execution.
2Quantity of substance
If traditional sparse matrix decomposition is used, then computation can be performed, but memory usage is high due to uncontrolled matrix block sizes
Solution Approach 1:
By segmenting the large sparse matrix into smaller sub-matrices arranged in a bordered-block diagonal structure, the patent reduces the memory footprint of each individual matrix block. This segmentation allows for more efficient memory management and enables parallel processing of smaller blocks, improving both memory utilization and computation speed.
Solution Approach 2:
The patent changes the structural parameters of the matrix by transforming it into a bordered-block diagonal form with specific partitioning. This parameter change optimizes the balance between memory usage and computation speed by controlling the size and distribution of non-zero elements in each sub-matrix block.
3Productivity
If distributed computing is employed, then parallel processing capability is improved, but communication between nodes increases
Solution Approach 1:
The patent segments the matrix into bordered-block diagonal form where each block can be processed by different compute nodes. The border structures in the partitioning minimize the coupling between sub-matrices, thereby reducing the amount of data that needs to be communicated between distributed nodes while maintaining parallel processing capability.
Solution Approach 2:
The patent extracts and separates the dominant diagonal blocks from the off-diagonal coupling elements. This extraction allows each compute node to independently process its assigned diagonal block with minimal communication requirements, reducing overall communication overhead in the distributed computing system.
Data Source
AI summary
A method and a system for large-scale linear circuit simulation, a circuit simulator and a storage medium are provided. The method includes: constructing ordinary differential equations for a linear circuit and converting the ordinary differential equations into a large-scale sparse system of linear equations; performing column reordering on a coefficient matrix of the large-scale sparse system of linear equations, obtaining a pre-reordered matrix; utilizing partitioning partition algorithm to perform row-column reordering, obtaining a doubly bordered-block diagonal matrix; employing a plurality of compute nodes, solving for local Schur complements of each of the distributed nodes, and summing up the local Schur complements to obtain a global Schur complement; solving for states of each of the distributed nodes at a current time step; and converting solution results from all time steps of each of the distributed nodes into a simulation result. The method significantly improves simulation efficiency while ensuring smooth simulation execution.