Sparse Computation Compression Circuit for Zero-Value Elimination
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Solution Overview
Problem
Digital systems face inefficiencies in processing large volumes of data due to the presence of zero values, which can be ignored but require hardware support for sparsity to achieve performance speed-ups, necessitating a method to eliminate or compress these values effectively.
Innovation Solution
A hierarchical compression technique using multiple stages of switches to remove zeros from data sets, compressing non-zero values to adjacent outputs and shifting them to ensure no overlap, thereby reducing area complexity and increasing sparsity levels and performance per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If zero values are removed from the data set to improve processing efficiency, then productivity is improved, but device complexity increases due to the need for special hardware support for sparsity
Solution Approach 1:
The patent extracts and removes zero values from the data set before processing, storing only non-zero values in a compressed format. This extraction of harmful elements (zeros) improves processing efficiency by eliminating unnecessary computations while the compression format manages the hardware complexity through efficient data representation
Solution Approach 2:
The patent changes the data representation parameter from standard format to a compressed sparse format. By transforming the data structure to store only non-zero values with their positions, the system achieves better processing efficiency while managing hardware requirements through parameter optimization
2Area of stationary object
If hierarchical compression technique is used to compress non-zero values, then area complexity is reduced, but device complexity increases due to multiple stages of switches
Solution Approach 1:
The patent divides the compression task into multiple hierarchical stages, with each stage handling a portion of the data. This segmentation allows the system to reduce area complexity by distributing the compression workload across multiple simpler stages rather than requiring a single complex compression unit
Solution Approach 2:
The patent introduces a hierarchical dimension to the compression architecture, organizing switches in multiple levels rather than a single flat structure. This dimensional organization reduces the area required for each individual stage while managing overall system complexity through structured hierarchy
3Productivity
If multiple stages of switches are used to remove zeros and compress data, then productivity is improved through faster processing, but device complexity increases due to additional switching components
Solution Approach 1:
The patent performs preliminary compression of data before it enters the main processing pipeline. By removing zeros and compressing non-zero values in advance through the hierarchical switch stages, the system improves processing speed for subsequent operations while managing complexity through the preliminary organization of data
Solution Approach 2:
The patent introduces compressed data format as an intermediary representation between the input data and the processing units. This intermediary format, created through the switching stages, enables faster processing by eliminating zeros while the structured compression approach manages the complexity of the switching components
Data Source
AI summary
Embodiments of the present disclosure include a digital circuit and method for compressing input digital values. A plurality of input digital values may include zero values and non-zero values. The input digital values are received on M inputs of a first switching stage. The first switching stage is arranged in groups that rearrange the non-zero values on first switching stage outputs according to a compression and shift. The compression and shift position the non-zero values on outputs coupled to inputs of a second switching stage. The second switching stage consecutively couples non-zero values to N outputs, where N is less than M.