Sparse Data Compression Circuit With Multi-Stage Bitmask Decompression
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Solution Overview
Problem
Modern digital systems face inefficiencies in processing large volumes of digital data due to the presence of numerous zero values, which lead to increased memory bandwidth overhead and computation burdens, particularly in AI applications where sparsity is a critical feature.
Innovation Solution
A hierarchical compression technique is employed, utilizing a multi-stage compression algorithm that stores sparse data sets with bit masks to reduce memory read and write times, allowing for faster data retrieval and processing by decompressing data into manageable sets that can be processed directly or further decompressed by processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is stored in uncompressed format in memory, then data retrieval is straightforward, but memory bandwidth overhead increases and memory transaction times increase
Solution Approach 1:
The patent segments data storage by separating non-zero values from zero values and using bit masks to indicate positions. This segmentation allows the system to store only essential data (non-zero values) along with positional information (bit masks), reducing overall memory bandwidth requirements while enabling efficient retrieval through selective decompression of only necessary data portions.
Solution Approach 2:
The patent extracts and removes redundant zero values from the data set, storing only non-zero values along with bit masks that indicate their original positions. This extraction eliminates unnecessary data transmission over the memory bus, directly reducing memory bandwidth overhead and transaction times while maintaining the ability to reconstruct the complete data set when needed.
2Loss of energy
If compression techniques are applied to sparse data sets, then memory bandwidth efficiency increases, but device complexity increases due to multi-stage compression and decompression algorithms
Solution Approach 1:
The patent applies preliminary compression action during data storage, transforming sparse data sets into a compact format with bit masks before writing to memory. This preliminary compression eliminates the need for decompression during subsequent read operations, as the compressed format with positional masks can be directly utilized by processing circuits, thereby reducing memory bandwidth overhead without requiring complex real-time decompression logic.
Solution Approach 2:
The patent introduces bit masks as an intermediary element that bridges the compressed data format and the processing requirements. These bit masks serve as a simple mediator that indicates the positions of non-zero values, allowing processing circuits to efficiently identify and operate on relevant data without requiring complex decompression algorithms, thus reducing device complexity while maintaining compression benefits.
3Reliability
If zero values are included in data processing, then complete data integrity is maintained, but computation burden increases and processing efficiency decreases
Solution Approach 1:
The patent extracts zero values from the data processing flow by using bit masks to identify and selectively process only non-zero values. This extraction maintains data integrity because the positional information in the bit masks ensures that non-zero values are correctly placed during reconstruction, while simultaneously eliminating computation burden by preventing processors from performing unnecessary operations on zero values.
Solution Approach 2:
The patent converts the presence of numerous zero values, which traditionally represents a harmful overhead for computation, into a benefit by using the sparsity pattern itself to create compact bit masks. These bit masks efficiently encode positional information, allowing the system to leverage the zero-value dominance as a feature rather than a bug, thereby improving both data integrity and computation efficiency.
Data Source
AI summary
Embodiments of the present disclosure include a digital circuit and method for multi-stage compression. Digital data values are compressed using a multi-stage compression algorithm and stored in a memory. A decompression circuit receives the values and performs a partial decompression. The partially compressed values are provided to a processor, which performs the final decompression. In one embodiment, a vector of N length compressed values are decompressed using a first bit mask into two N length sets having non-zero values. The two N length sets are further decompressed using two M length bit masks into M length sparse vectors, each having non-zero values.