Sparse-Dense Matrix Accelerator for Asymmetric Multiplication

The patent applies asymmetry by designing an instruction set architecture that explicitly supports asymmetric sparse-dense matrix multiplication operations. The SDMM instruction allows the first operand to be sparse while the second operand remains dense, removing the symmetry requirement of traditional architectures. This enables the processor to efficiently handle operations where only one matrix exhibits sparsity patterns, thereby leveraging sparsity to improve computational performance without requiring both inputs to have the same density structure.

The patent applies parameter changes by modifying the operational parameters of matrix multiplication to accommodate sparse-dense asymmetric inputs. The SDMM instruction changes the density parameter of the first operand to sparse while keeping the second operand dense, allowing the system to optimize for sparsity patterns. This parameter change enables the processor to skip operations on zero elements in the sparse matrix, thereby improving throughput by a factor proportional to the sparsity ratio without complicating the operational interface.

The patent applies segmentation by dividing the matrix multiplication operation into distinct phases: sparse matrix loading, sparsity pattern identification, selective multiplication for non-zero elements only, and accumulation. The SDMM instruction segments the computational workflow to process only the non-zero elements of the sparse matrix, thereby improving throughput. This segmentation is implemented through specialized execution circuitry that handles sparse-dense multiplication differently from traditional dense-dense multiplication, achieving higher productivity while adding targeted complexity only where needed for sparsity exploitation.