Sparse Drive Control Circuit for High-Refresh Light-Field Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional drive modes for light-field display technologies, such as passive and active addressing, fail to meet the high refresh frame rate requirements, and static scanning drive modes are costly and difficult to implement due to large drive chips and complex wiring.
Innovation Solution
A drive control circuit with a decoding and control unit, decoding and gating units, and drive sources, along with a sparse drive method that selectively drives only necessary light-emitting structures, achieving high refresh rates and reduced bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional drive modes (passive addressing, active addressing, dynamic scanning) are used, then device complexity is low, but refresh frame rate is insufficient (60-3.8 KHz) for light-field display requirements (30 KHz)
Solution Approach 1:
The drive control circuit is divided into multiple independent cell blocks (e.g., 4×4=16 blocks), each capable of autonomous operation with its own decoding and gating units. This segmentation allows parallel driving of multiple pixel groups, achieving high refresh rates (30 KHz) without requiring a monolithic complex drive circuit
Solution Approach 2:
The patent implements sparse driving where only M1 drive signal output ends (M1 < N1) are actively driven at any given time based on preset information. This partial action approach achieves the required refresh frame rate while reducing bandwidth requirements and simplifying the effective drive circuit complexity
2Productivity
If static scanning drive mode is used to achieve high refresh frame rates (30 KHz), then productivity requirement is met, but device complexity increases due to excessively large drive chip and difficult wiring
Solution Approach 1:
The drive control circuit is divided into multiple independent cell blocks (e.g., 4×4=16 blocks), each capable of autonomous operation with its own decoding and gating units. This segmentation allows parallel driving of multiple pixel groups, achieving high refresh rates (30 KHz) without requiring a monolithic complex drive circuit
Solution Approach 2:
The patent organizes cell blocks in a two-dimensional array (M2 rows × N2 columns) with row and column gating circuits, adding spatial dimensionality to the drive architecture. This dimensional organization reduces wiring complexity compared to a flat hierarchical structure while enabling efficient parallel control of all cell blocks
3Reliability
If all N1 drive signal output ends are driven simultaneously, then complete display coverage is achieved, but bandwidth requirements become excessively large
Solution Approach 1:
The patent implements sparse driving where only M1 drive signal output ends (M1 < N1) are actively driven at any given time based on preset information. This partial action approach achieves the required refresh frame rate while reducing bandwidth requirements and simplifying the effective drive circuit complexity
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The present disclosure describes a drive control circuit, a drive control chip, an integrated packaged device, a display system, and a sparse drive method. The drive control circuit includes a data input end, a clock input end, a decoding and control unit, a decoding and gating unit, at least two drive sources, and at least two drive signal output ends. A first input end of the decoding and control unit is electrically connected to the data input end, a second input end is electrically connected to the clock input end, a control input end is electrically connected to a control output end, an address input end is electrically connected to an address output end.