Low-Latency Lookup Circuit Using Sparse Hash Functions
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Solution Overview
Problem
Existing hardware implementations of lookup tables in computer networking devices face challenges in achieving low latency and high memory capacity while managing power consumption and key size limitations, particularly in solving the longest-prefix match problem, and software approaches lack efficiency in parallel processing.
Innovation Solution
The implementation of programmable hash tables using hardware circuitry that evaluates hash functions by multiplying input bit vectors with sparse bit matrices, allowing for low-latency lookups and flexible key sizes, with hash functions pre-computed in software and transferred to hardware for efficient evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If TCAMs are used for low-latency lookups, then access latency is reduced, but memory capacity decreases and power consumption increases
Solution Approach 1:
The patent divides the lookup table into multiple segments stored in standard SRAM, with each segment having dedicated comparator logic. This segmentation allows the system to achieve TCAM-like low-latency access for each segment while maintaining much higher overall memory capacity in standard SRAM technology.
Solution Approach 2:
The patent combines standard SRAM memory with comparator logic circuits to create a hybrid structure that merges the high capacity of SRAM with the fast access capability of TCAM. Multiple SRAM segments are combined with parallel comparator arrays to achieve both high capacity and low latency.
2Loss of time
If TCAMs are used for low-latency lookups, then access latency is reduced, but power consumption increases
Solution Approach 1:
The patent segments the comparator logic into multiple independent units, each serving a specific SRAM segment. This allows the system to activate only the necessary comparator segments during operation, reducing overall power consumption while maintaining fast access latency for the active segments.
Solution Approach 2:
The patent applies comparator logic locally to specific SRAM segments rather than globally to the entire memory array. This local application of comparison functionality reduces the total number of active comparators and their associated power consumption while preserving fast access characteristics.
3Quantity of substance
If tree-based TRIE structures are used in SRAM, then memory capacity increases, but lookup latency increases due to multiple memory accesses
Solution Approach 1:
The patent segments the key comparison operation into parallel operations across multiple SRAM segments. Instead of sequential traversal through multiple memory levels as in TRIE structures, the system divides the key space and performs simultaneous comparisons across segmented SRAM arrays, achieving both high capacity and low latency.
Solution Approach 2:
The patent pre-organizes the SRAM segments and their associated comparator logic to enable direct parallel comparison of key segments. This preliminary organization of data and logic structures allows the system to perform multiple comparisons simultaneously in a single access cycle, avoiding the sequential multiple accesses required by tree-based structures.
4Quantity of substance
If standard SRAM is used instead of TCAM, then memory capacity increases, but access latency increases
Solution Approach 1:
The patent merges standard SRAM memory arrays with dedicated comparator logic circuits to create a hybrid structure that achieves both the high capacity of SRAM and the fast access of TCAM. The comparator logic is integrated directly with the SRAM segments to enable rapid comparison operations.
Solution Approach 2:
The patent divides the SRAM memory into multiple segments, each with its own dedicated comparator logic. This segmentation enables parallel comparison operations across multiple segments simultaneously, achieving low overall latency while maintaining high total memory capacity in standard SRAM technology.
Data Source
AI summary
A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit may multiply bit vectors representing key values by a sparse bit matrix and may add a constant bit vector to the results. The hash function sub-circuits may be constructed using odd-parity circuits that accept as inputs subsets of the bits of the bit vectors representing the key values. The sparse bit matrices may be chosen or generated so that there are at least twice as many 0-bits per row as 1-bits or there is an upper bound on the number of 1-bits per row. Using sparse bit matrices in the hash function sub-circuits may allow the lookup circuit to perform lookup operations with very low latency.