Sparse Logistic Regression for Circuit Mismatch Variation Analysis
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Solution Overview
Problem
Current circuit simulation methods are inefficient in capturing mismatch variation contributions, particularly at finer feature sizes, as they require extensive computational resources and do not provide sufficient information for designers to optimize circuit performance effectively.
Innovation Solution
A computer-implemented method using sparse logistic regression and cross-validation to model mismatch contribution, allowing for the identification of critical devices impacting circuit performance and reducing the number of required simulations through optimized modeling and sizing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional OFAT sensitivity analysis is used to model mismatch variation, then each mismatch parameter can be analyzed individually, but the computational expense becomes prohibitive requiring thousands of Monte Carlo simulations
Solution Approach 1:
The patent segments the circuit into individual devices and further segments the analysis into mismatch parameter-level contributions. By computing mismatch contribution at the device parameter level rather than circuit level, and by identifying and focusing on the most significant contributors, the method divides the computational task into manageable segments that require far fewer simulations than traditional OFAT analysis
Solution Approach 2:
The patent extracts and identifies the most significant mismatch contributors from the circuit using sensitivity analysis and statistical methods. By taking out only the critical devices and parameters that contribute most to output variation, the method eliminates the need to analyze all devices equally, thereby reducing the number of required simulations while maintaining analysis accuracy
2Productivity
If simple linear sensitivity analysis is used, then computational resources are reduced, but insufficient information is provided for designers to fully optimize the design
Solution Approach 1:
The patent applies local quality by providing detailed mismatch contribution information at the device and parameter level rather than aggregate circuit-level information. This localized detailed information about which specific devices and parameters contribute most to variation enables designers to make targeted optimizations at critical locations in the circuit, improving design efficiency while maintaining comprehensive information about device impacts
3Reliability
If comprehensive mismatch analysis of all devices is performed, then complete information about circuit performance variation is obtained, but the computational expense becomes significant or prohibitive
Solution Approach 1:
The patent applies partial action by performing mismatch analysis only on the most significant contributors identified through sensitivity analysis and statistical screening, rather than analyzing all devices in the circuit. By focusing computational resources on the critical subset of devices that have the greatest impact on output variation, the method achieves reliable performance prediction with significantly reduced computational expense
Data Source
AI summary
A system, method, and computer program product for predicting mismatch contribution in an electronic environment. Embodiments may include modeling, using a processor, a discrete output mismatch contribution problem using sparse logistic regression to generate a mismatch contribution model and applying a cross-validation approach to increase a complexity of the mismatch contribution model. Embodiments may further include computing one or more mismatch contribution values from the mismatch contribution model and defining at least one sizing constraint or determining a worst case result associated with a sampling process based upon, at least in part, the one or more mismatch contribution values.