Sparse Matrix Accelerated Computing via Non-Zero Detection
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Solution Overview
Problem
Existing matrix product operations in sparse matrices are slow due to software-based implementations, leading to inefficient use of on-chip resources and inability to meet real-time processing requirements.
Innovation Solution
A sparse matrix accelerated computing method that involves non-zero detection of sparse matrices, generating status information, storing non-zero data in RAM, and performing logical operations to optimize product matrix calculations, thereby reducing resource usage and improving processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software-based matrix product operations are used, then implementation flexibility is maintained, but processing speed is slow and real-time requirements cannot be met
Solution Approach 1:
The patent replaces software-based matrix operations with a hardware accelerator that uses parallel computing units and dedicated circuits to perform sparse matrix multiplication, thereby achieving real-time processing speeds while maintaining implementation flexibility through configurable hardware architecture
Solution Approach 2:
The patent divides the sparse matrix into non-zero elements and zero elements, processes non-zero elements through parallel computing units while skipping zero elements, and uses status registers to track processing states, thereby achieving high-speed processing without unnecessary computations
2Speed
If entire sparse matrices are stored in on-chip memory, then fast access is achieved, but on-chip resource usage increases significantly
Solution Approach 1:
The patent extracts only the non-zero elements from the sparse matrix and stores them in on-chip memory, while zero elements are handled through status register operations. This extraction approach enables fast access to relevant data while minimizing on-chip memory consumption by storing only essential information
Solution Approach 2:
The patent transforms the traditional two-dimensional matrix storage by using status registers to encode the positions and states of matrix elements. This dimensional transformation allows the system to track matrix state information efficiently without requiring proportional increases in on-chip memory resources
3Productivity
If non-zero detection and status register operations are implemented, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent designs status registers that serve multiple functions: tracking non-zero element positions, storing processing states, and controlling data flow to computing units. This multi-functionality improves processing efficiency while minimizing the increase in device complexity by using the same hardware structure for multiple purposes
Data Source
AI summary
A sparse matrix accelerated computing method and apparatus, a device, and a medium are disclosed. The method includes: reading and performing non-zero detection on a first sparse matrix, and generating first status information of each line of data of the first sparse matrix by the detection result and storing same into a register; storing non-zero data of the first sparse matrix into an RAM; reading and performing non-zero detection on a second sparse matrix, and generating second status information of each row of data of the second sparse matrix by a detection result and storing same into the register; and performing a logical operation on the first status information and the second status information, reading the data in the RAM by the logical operation result, and performing a product operation on the data in the RAM and data of the second sparse matrix to obtain product matrix data.