Sparse Matrix Arithmetic Hardware Using Bitmap Scheduling
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Solution Overview
Problem
Current computing systems face significant limitations due to the 'memory wall' issue, where the gap between processing capabilities and memory bandwidth leads to inefficiencies, particularly in performing arithmetic operations on sparse matrices, as they require loading and processing zero fill values, which consume bandwidth and power without contributing to results.
Innovation Solution
The hardware includes a scheduler that generates a schedule of instructions and addresses from a bitmap indicating zero or non-zero matrix entries, allowing only non-zero values to be processed, thereby eliminating unnecessary operations and reducing memory bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory systems are used to store and process sparse matrices, then data can be accessed and processed, but memory bandwidth is wasted on transferring zero fill values and processing time increases due to unnecessary operations
Solution Approach 1:
The patent extracts and removes zero fill values from the sparse matrix data structure before transfer to the processor. By using a compressed sparse row format that stores only non-zero elements with their corresponding column indices and row offsets, the system eliminates unnecessary data transfer of zero values, thereby reducing memory bandwidth consumption while maintaining processing speed
Solution Approach 2:
The patent segments the sparse matrix into blocks and uses a bitmap to indicate which blocks contain non-zero elements. This segmentation allows the system to selectively process only relevant blocks, avoiding transfer and processing of blocks that are entirely zero, thus improving productivity while reducing energy loss
2Reliability
If zero fill values are included in sparse matrix operations, then the matrix structure is maintained, but unnecessary arithmetic operations are performed consuming power and time
Solution Approach 1:
The patent extracts zero fill values from the computation process by using a compressed representation that stores only non-zero elements. The bitmap and compressed data structures enable the processor to skip zero elements entirely during arithmetic operations, eliminating wasted computation time while maintaining computational accuracy through proper handling of the compressed format
Solution Approach 2:
The patent performs preliminary compression of the sparse matrix into a compressed sparse row format with bitmaps before the actual arithmetic operations. This preliminary action organizes the data structure to explicitly mark zero and non-zero regions, allowing subsequent operations to quickly identify and process only relevant data, thereby reducing operation time without compromising accuracy
3Loss of energy
If compressed memory subsystems are used to reduce memory bandwidth usage, then bandwidth efficiency improves, but additional memory capacity and register file pressure are required for decompression
Solution Approach 1:
The patent implements self-service by performing compression and decompression operations directly within the coprocessor unit that handles sparse matrix computations. The compressed sparse row data structure is designed to be processed in-place by the specialized hardware, eliminating the need for separate decompression stages and reducing overall system memory capacity requirements while maintaining bandwidth efficiency
Data Source
AI summary
Hardware for performing sequences of arithmetic operations. The hardware comprises a scheduler operable to generate a schedule of instructions from a bitmap denoting whether an entry in a matrix is zero or not. An arithmetic circuit is provided which is configured to perform arithmetic operations on the matrix in accordance with the schedule.