Sparse Matrix Mask Bit Expansion in Renamer Registers
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Solution Overview
Problem
Existing methods for parallelizing arithmetic operations on sparse matrices using SIMD techniques face challenges with mask pattern generation, leading to logical register depletion and processing speed decreases due to dependency relationships when using renamers.
Innovation Solution
The processor employs a renamer to set and expand mask bits in physical registers, breaking down mask registers bit-by-bit and allocating them to different physical registers to manage mask operations efficiently, thereby reducing logical register usage and resolving dependency relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If mask pattern generation is performed using existing SIMD techniques, then parallelization of sparse matrix operations is achieved, but logical register depletion occurs and processing speed decreases
Solution Approach 1:
The mask register is segmented into multiple individual mask bits, each representing a separate mask pattern. Instead of generating multiple mask registers, the system divides the mask register into bits (e.g., bit 0, bit 1, bit 2, etc.), where each bit can independently represent a different mask pattern for parallel operations on sparse matrices with varying row element counts.
Solution Approach 2:
The invention transitions from using multiple mask registers (spatial dimension) to using multiple mask bits within a single register (bit-level dimension). This dimensional shift allows the system to represent multiple mask patterns simultaneously within the same physical register space, effectively resolving the logical register depletion issue while maintaining parallelization capabilities.
2Adaptability or versatility
If renamer is used to manage mask operations, then mask pattern generation is enabled, but dependency relationships cause processing speed to decrease
Solution Approach 1:
The invention extracts the mask pattern representation from the renamer's register allocation system and places it directly into the mask register bits. By taking out the mask pattern generation function from the renamer, the system eliminates the dependency relationships that the renamer introduces, allowing mask operations to proceed without the processing speed penalties associated with renamer dependency management.
Solution Approach 2:
Instead of using the renamer to dynamically generate and manage mask patterns, the system pre-defines multiple mask patterns by setting specific combinations of mask bits. This copying approach replicates the functionality of dynamic mask generation through static bit configurations, eliminating runtime dependencies while maintaining adaptability for different sparse matrix structures.
Data Source
AI summary
A non-transitory computer-readable recording medium stores an arithmetic processing program for causing a computer to execute a process including: setting, in a mask register used for a mask operation, to each of a plurality of mask bits that indicates a bit corresponding to each element of each row of a sparse matrix, each mask pattern for designating the mask operation; and expanding the plurality of mask bits to which the respective mask patterns are set to different areas of a physical register, respectively.