Sparse Matrix Multiplier Circuit for CGRA Efficiency
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Solution Overview
Problem
Traditional matrix multiplication methods are inefficient when dealing with sparse matrices, particularly in machine learning and high-performance computing applications, due to the inefficiency of processing matrices mostly populated with zero values.
Innovation Solution
A method utilizing a Coarse-Grained Reconfigurable Architecture (CGRA) to efficiently perform sparse matrix multiplication by compressing the sparse matrix into col_indices, values, and nnzs_per_row vectors, and then processing these vectors through an index stage, multiply stage, and index add stage to generate the product matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional matrix multiplication methods are used on sparse matrices, then the computation is performed on all elements including zeros, but this results in wasted computational resources and reduced efficiency
Solution Approach 1:
The patent extracts only the non-zero elements from the sparse matrix, storing them in a compressed format with their corresponding row and column indices. This extraction eliminates the need to process zero elements during multiplication, directly addressing the inefficiency of traditional methods by removing unnecessary computational operations.
Solution Approach 2:
The patent segments the sparse matrix into three separate vectors: row indices, column indices, and non-zero values. This segmentation allows the multiplication algorithm to process only relevant data elements, avoiding iteration over zero elements and thereby improving computational efficiency while reducing energy consumption.
2Productivity
If sparse matrices are stored in traditional dense format, then the storage structure is simple, but this results in increased memory usage and inefficient processing
Solution Approach 1:
The patent extracts only the non-zero elements from the sparse matrix for storage, creating a compressed sparse row (CSR) format. This extraction reduces the quantity of data that must be stored in memory from N×M elements to only the non-zero elements, directly addressing the inefficiency of storing and processing zeros.
Solution Approach 2:
The patent segments the matrix storage into three separate arrays: row pointers, column indices, and non-zero values. This segmentation enables efficient memory access patterns during multiplication, allowing the algorithm to skip over zero elements without requiring additional memory for their storage.
3Productivity
If general-purpose processors are used for machine learning workloads, then the architecture is flexible and programmable, but this results in insufficient performance for complex deep learning applications
Solution Approach 1:
The patent employs a reconfigurable processor architecture that can dynamically change its configuration to match the specific requirements of different machine learning workloads. This dynamic reconfigurability allows the processor to optimize its structure for sparse matrix operations when needed, achieving high performance for complex deep learning applications while maintaining architectural flexibility.
Solution Approach 2:
The patent designs a universal reconfigurable processor that can perform multiple functions including sparse matrix multiplication, dense matrix operations, and other computational tasks. This multi-functionality is achieved through reconfigurable compute units and interconnect structures that can be programmed to execute different algorithms, addressing both performance and flexibility requirements.
Data Source
AI summary
The technology disclosed relates to matrix multiplication where the multiplier can be a sparse matrix. In particular, a multiplication device includes first circuitry configured to obtain the multiplicand matrix and an index of columns of the multiplier matrix and to generate an intermediate matrix that has one row per entry in the index copied from a respective row of the multiplicand matrix based on a value of a corresponding entry in the index. The device also includes second circuitry configured to receive the intermediate matrix from the first circuitry, obtain non-zero values of the multiplier matrix and a list of a number of non-zero entries per row of the multiplier matrix, and generate a product matrix as a result of multiplies of the non-zero values of the multiplier matrix and the intermediate matrix.