Sparse Matrix Partition Compression for Vector Processing

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Solution Overview

Problem

Existing systems face challenges in efficiently processing sparse matrices due to high memory and bandwidth requirements, irregularity, and complexity in execution, which limits throughput in digital signal processing and neural networks.

Innovation Solution

The method involves partitioning a sparse matrix into smaller partitions, compressing each partition by identifying and grouping non-zero elements with their column indices into ordered sets, and using vector processors to perform parallel multiply-and-accumulate operations, allowing for efficient storage and processing of sparse matrices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If parallel matrix multiplier circuitry is used to speed up processing, then processing speed is improved, but data movement between RAM resources and on-chip hardware accelerator memory limits throughput and consumes significant circuit and computing resources

Engineering Contradiction:
Improveprocessing speedVSAvoidcircuit and computing resources
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The matrix is divided into multiple partitions, each processed independently by separate vector processors. This segmentation allows parallel processing of matrix partitions while reducing the memory bandwidth requirements for each individual processor, as each processor handles a smaller subset of the data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the traditional row-major or column-major storage format into a compressed format organized by non-zero element positions (row indices and column indices). This dimensional reorganization allows the system to skip over zero elements during computation, reducing the effective data movement volume without sacrificing processing parallelism.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If intelligent sparsification is applied to reduce computation and memory bandwidth requirements, then resource usage is reduced, but sparsity introduces irregularity and extra complexity in execution

Engineering Contradiction:
Improvememory bandwidth requirementsVSAvoidexecution complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The sparse matrix is pre-processed into a compressed format where non-zero elements are identified and their positions (row indices and column indices) are recorded before the actual matrix-vector multiplication. This preliminary organization eliminates the need for complex runtime checks to identify non-zero elements, simplifying the execution phase while maintaining the benefits of sparsity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the representation parameters of the matrix from a dense grid format to a compressed format defined by non-zero element values, their row indices, and column indices. This parameter transformation reduces the data volume to be processed and allows the execution logic to focus only on meaningful computations.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the entire sparse matrix is stored and processed, then complete accuracy is maintained, but memory and bandwidth requirements become prohibitively high

Engineering Contradiction:
Improvecomputation accuracyVSAvoidmemory requirements
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the non-zero elements from the sparse matrix and stores them in a compressed format along with their position indices. By removing the zero elements entirely from storage and computation, the memory requirements are dramatically reduced while the computational accuracy is preserved, as all non-zero contributions to the matrix-vector product are retained.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20240193227A1Compression of sparse matrices for vector processing
Publication Date: 2024.06.13 XILINX INC
  • US20240193227A1 patent drawing
  • US20240193227A1 patent drawing
  • US20240193227A1 patent drawing

AI summary

Partition-level compression of an m×n sparse matrix includes determining in each partition, row and column indices of elements having non-zero values. Each partition has s rows and t columns and s<m and t<n. A group of ordered sets of tuples is generated from the elements and row and column indices in each partition that has at least one non-zero element. Each ordered set includes s tuples, and positions of the s tuples in the ordered set correspond to the s rows of the partition, each tuple includes a value of an element of the partition and an associated column index, and the associated column index indicates, for an element of the partition having a non-zero value, a column index in the partition. A compression processor indicates for each group, a count of the one or more ordered sets, a partition row number, and a partition column number.