Sparse Distributed Memory Using Memristive In-Memory Similarity Search
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing implementations of sparse distributed memory (SDM) face challenges such as large circuit size, high power consumption, and limited throughput capacity, particularly when translated to hardware-based architectures, and suffer from latency bottlenecks and inefficiencies in data movement between data and storage units.
Innovation Solution
Implementing a memristive-based SDM system using a dot product engine (DPE) and content addressable memory (CAM) architecture, which performs in-memory computing operations, reduces data movement and latency by utilizing programmable resistors like memristors to perform bitwise sum calculations and similarity comparisons directly in memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional hardware-based architectures (adders, decoders, counters, digital logic) are used to implement SDM, then the system can perform basic SDM operations, but the circuit size becomes large and power consumption increases
Solution Approach 1:
The patent replaces conventional digital logic circuits (adders, decoders, counters) with a hardware neural network architecture that uses memristive devices and crossbar arrays to perform SDM operations through analog computation and parallel processing, thereby reducing circuit size and power consumption
Solution Approach 2:
The hardware neural network architecture is designed to perform multiple SDM operations (storage, retrieval, pattern recognition, noise filtering) using a unified structure of crossbar arrays and memristive devices, eliminating the need for separate dedicated circuits for each function
2Productivity
If conventional hardware-based architectures are used to implement SDM, then the system can process data, but throughput capacity is limited and latency bottlenecks occur
Solution Approach 1:
The system pre-loads data into the crossbar array memory structure, enabling rapid retrieval and processing without repeated data movement between storage and processing units, thereby reducing latency
Solution Approach 2:
The hardware neural network performs parallel computations across all neurons simultaneously, maintaining continuous processing without the sequential bottlenecks of conventional architectures, thereby increasing throughput capacity
3Productivity
If data is moved between storage units and processing units in conventional architectures, then computation can be performed, but processing efficiency decreases due to data movement overhead
Solution Approach 1:
The patent merges storage and processing functions into a single integrated hardware neural network structure where memristive devices store weights and crossbar arrays perform computations in-place, eliminating the need for data movement between separate storage and processing units
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a compact, low-latency SDM architecture that enhances parallel processing capabilities, reduces processing bottlenecks, and eliminates the need for analog-to-digital conversions, achieving high-speed access and efficient data retrieval.
Implementation Method 1
Implementing a memristive-based SDM system using a dot product engine (DPE) and content addressable memory (CAM) architecture, which performs in-memory computing operations, reduces data movement and latency by utilizing programmable resistors like memristors to perform bitwise sum calculations
Data Source
AI summary
A device for implementing sparse distributed memory may include first circuitry having a plurality of cells arranged in first subsets. The first circuitry may be configured to receive a first input vector for a write operation and calculate a similarity between the first subsets of the first circuitry and the first input vector. The device may include second circuitry coupled to the first circuitry and configured to output a first activation signal. The device may include third circuitry coupled to the second circuitry and having cells arranged in second subsets. The third circuitry may be configured to receive the first activation signal and selectively activate one or more first selected subsets of the second subsets in response to the first activation signal by incrementing or decrementing corresponding values of the cells of the one or more first selected subsets based on the first input vector.