Sparse Tensor Storage Layout for Neural Network Accelerator Data Transfer

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Solution Overview

Problem

Neural network accelerators face inefficiencies due to the lack of consideration for sparsity in tensor storage, leading to increased memory usage, power consumption, and processing delays, especially when tensors need to be rotated and transferred between compute units.

Innovation Solution

Implementing sparse tensor storage by compressing tensor data based on sparsity, rotating tensors within the accelerator, and replicating only required border regions, allowing for efficient storage and transfer of data in a format optimized for neural network computations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If dense tensor storage is used without considering sparsity, then memory allocation is simplified, but memory usage and power consumption increase

Engineering Contradiction:
Improvememory allocation complexityVSAvoidmemory usage
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent extracts and stores only the non-zero elements of sparse tensors along with their coordinate information, separating useful data from redundant zero elements. This extraction approach reduces memory usage while maintaining the ability to perform computations on sparse tensors efficiently.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies different storage strategies to different regions of tensor data based on sparsity patterns. By identifying and storing only non-zero elements in specific coordinate positions, the system optimizes memory usage for sparse regions while maintaining dense storage where appropriate.

Inventive Principle:
Principle #3Local quality

2Ease of operation

If dense tensor storage is used without considering sparsity, then data transfer between compute units is simplified, but power consumption increases

Engineering Contradiction:
Improvedata transfer simplicityVSAvoidpower consumption
Core Design Contradiction:
Ease of operationVSUse of energy by stationary object

Solution Approach 1:

The patent extracts and transfers only non-zero tensor elements between compute units, reducing the volume of data that needs to be transmitted. This extraction of essential information maintains computational accuracy while reducing power consumption during data transfer operations.

Inventive Principle:
Principle #2Taking out (Extraction)

3Shape

If full tensor rotation is performed, then tensor orientation is correctly adjusted, but processing delays increase

Engineering Contradiction:
Improvetensor orientationVSAvoidprocessing delays
Core Design Contradiction:
ShapeVSLoss of time

Solution Approach 1:

The patent extracts and rotates only the non-zero elements of sparse tensors rather than performing full tensor rotation. By identifying non-zero elements and rotating only those with their coordinate transformations, the system achieves correct tensor orientation while significantly reducing processing time.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the tensor rotation operation into identifying non-zero elements, extracting them, rotating their coordinates, and reassembling the rotated sparse tensor. This segmentation allows the system to avoid processing zero elements, reducing overall rotation time while maintaining correctness.

Inventive Principle:
Principle #1Segmentation

4Productivity

If border regions are replicated for all compute units, then parallel processing is facilitated, but memory usage increases

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidmemory usage
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent applies border region replication selectively based on sparsity patterns and computational requirements of different compute units. By analyzing which compute units actually need border data from neighboring regions, the system replicates only necessary border elements, maintaining parallel processing capability while reducing redundant memory usage.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP4109763A1Methods and apparatus for sparse tensor storage for neural network accelerators
Publication Date: 2022.12.28 INTEL CORP
  • EP4109763A1 patent drawingFigure 1
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  • EP4109763A1 patent drawingFigure 3

AI summary

Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.