Sparse Vector-Matrix Multiplication Using Coaxial Nanowires
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Solution Overview
Problem
Existing dot-product engines require O(n^2) spatial resources on-chip for storing parameter values, leading to an undesirable trade-off between computation time efficiency and on-chip area.
Innovation Solution
A sparse vector-matrix multiplication system using a silicon substrate with a circuit layer, electrodes, and a randomly formed mesh of coaxial nanowires, where the circuit layer converts digital input signals to analog signals and modulates the resistances of the nanowires to perform efficient vector-matrix multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional dot-product engines are used to achieve O(n) computation time scaling, then computation speed is improved, but on-chip area scales quadratically as O(n^2)
Solution Approach 1:
The patent segments the dense crossbar array into multiple sparse sub-arrays, where each sub-array handles a portion of the matrix multiplication. This segmentation allows the system to maintain O(n) computation time while reducing the total on-chip area by exploiting the sparsity of typical matrix operations in applications like neural networks.
Solution Approach 2:
The patent employs dynamic configuration of the crossbar array, where the connectivity and activation of individual crosspoints can be dynamically adjusted based on the sparsity pattern of the input matrices. This dynamic adaptation allows the system to optimize between computation speed and area usage depending on the specific workload characteristics.
2Loss of time
If dense crossbar matrices are used to store parameter values, then O(n) computation time is achieved, but spatial resources scale as O(n^2)
Solution Approach 1:
The patent extracts and removes the redundant zero-value connections from the dense crossbar matrix, keeping only the non-zero elements that contribute to the computation. This extraction of essential elements reduces the spatial resources required while maintaining the O(n) computation time scaling by preserving the critical computational paths.
Solution Approach 2:
The patent applies local quality by assigning different connectivity densities to different regions of the crossbar array based on the sparsity pattern of the specific computation. Regions with higher non-zero element density are allocated more resources, while sparse regions use fewer resources, optimizing the balance between computation time and spatial resources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system achieves O(n) scaling in computation time and spatial resources, reducing the quadratic scaling issue of traditional dot-product engines and optimizing chip area usage.
Implementation Method 1
the non-volatile memory material includes a voltage-controlled resistance
Data Source
AI summary
Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.