Sparsely-Bonded CMOS Hybrid Imager Interconnect Reduction
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Solution Overview
Problem
Conventional hybrid imagers require a large number of interconnects, leading to manufacturing challenges and inefficiencies, such as high yield defects and limited pixel size due to the need for one interconnect per pixel, and the electronics surrounding the imaging array making it difficult to create large mosaic arrays.
Innovation Solution
A sparsely-bonded hybrid technology where the full pixel, including photodiodes and transistors, is integrated onto the Detector Array, reducing interconnects to one per column and two per row, allowing for a compact and robust imaging system with virtually all exposed silicon being optically active.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one interconnect per pixel is used in conventional hybrid imagers, then each pixel can be individually connected to the ROIC, but the number of interconnects becomes extremely large (one million for a one million pixel array), leading to high manufacturing defects and limited pixel size
Solution Approach 1:
The pixel array is segmented into regions that share common readout circuitry. Instead of connecting each pixel individually to the ROIC, pixels are grouped and share column and row readout paths, reducing the interconnect count from one per pixel to one per column and one per row.
Solution Approach 2:
The readout circuitry is designed with universal functionality where the same readout channels serve multiple pixels. The column and row readout circuits can handle signals from multiple pixels simultaneously, allowing one interconnect to serve many pixels rather than requiring dedicated interconnects for each pixel.
2Area of stationary object
If electronics surround the imaging array in conventional hybrid imagers, then signal processing and control functions are integrated, but this makes it difficult to create large mosaic arrays and increases the dead zone area
Solution Approach 1:
The readout circuitry is moved from surrounding the imaging array in the same plane to being positioned behind the detector array in a different dimensional arrangement. This allows the imaging array to be maximized in the front plane while readout electronics are accessed from the back, eliminating the need for large dead zones around the array perimeter.
3Area of moving object
If pixel size is reduced to increase array density, then more pixels can be packed into the same area, but the interconnect spacing becomes the limiting factor in conventional hybrid imagers
Solution Approach 1:
The imaging array is divided into a grid structure with column and row segments that share common readout paths. This segmentation allows pixels to be packed densely without requiring proportional increases in interconnect density, as multiple pixels share the same readout channels.
Solution Approach 2:
Column and row readout circuits act as intermediary elements between the densely packed pixels and the final output. Instead of direct one-to-one connections, these intermediary circuits aggregate and process signals from multiple pixels, allowing pixel density to exceed interconnect density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of interconnects, increases manufacturing yield, enables smaller pixel sizes, and allows for the creation of large, compact imagers with improved sensitivity and efficiency by decoupling pixel size from interconnect spacing.
Implementation Method 1
Light falling on a pixel liberates electric charge which is then converted in to a signal voltage
Data Source
AI summary
A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.