Configurable Spatial Accelerator Using Dataflow Graph Overlay

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Solution Overview

Problem

Exascale computing requires significant system-level floating point performance within a tight power budget, which classical von Neumann architectures struggle to achieve due to high energy costs associated with out-of-order scheduling and complex register files.

Innovation Solution

A configurable spatial accelerator (CSA) with an array of low-complexity, energy-efficient processing elements connected by lightweight, back-pressured networks, executing dataflow graphs directly rather than transforming them into sequential instruction streams, and utilizing dataflow operators and latency-insensitive channels for efficient data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If classical von Neumann architectures are used to achieve exascale computing, then system-level floating point performance can be improved, but power consumption increases significantly due to out-of-order scheduling and complex register files

Engineering Contradiction:

Improvesystem-level floating point performanceVSAvoidpower consumption

Core Design Contradiction:

PowerVSUse of energy by moving object

Solution Approach 1:

The processor is divided into multiple processing lanes (e.g., 8 lanes), each capable of independent instruction execution. This segmentation allows parallel processing of multiple instruction streams, achieving high floating point performance without requiring complex out-of-order scheduling logic in each lane, thereby reducing power consumption per lane while maintaining aggregate performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each processing lane is designed with universal functionality to execute multiple instruction types (integer, floating-point, vector operations) through a common execution core structure. This multi-functionality eliminates the need for specialized hardware for each operation type, reducing overall system complexity and power consumption while maintaining exascale computing capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If out-of-order scheduling and complex register files are implemented, then instruction execution efficiency is improved, but device complexity and power consumption increase

Engineering Contradiction:

Improveinstruction execution efficiencyVSAvoidcomplexity of scheduling and register files

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The register file system is segmented into lane-specific register files, with each processing lane having its own dedicated register file. This eliminates the need for complex cross-lane register allocation and scheduling logic, simplifying the control structure while maintaining high instruction execution efficiency through parallel access to lane-specific registers.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each processing lane operates as a self-contained execution unit with its own instruction pointer, register file, and execution logic. This self-service architecture allows each lane to independently fetch, decode, and execute instructions without requiring complex inter-lane coordination or centralized scheduling, thereby reducing device complexity while maintaining productivity.

Inventive Principle:

Principle #25Self-service

3Adaptability or versatility

If traditional processor architectures are used, then compatibility with existing instruction sets is maintained, but energy efficiency and performance per watt are insufficient for exascale requirements

Engineering Contradiction:

Improvecompatibility with instruction setsVSAvoidenergy efficiency

Core Design Contradiction:

Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The processor supports dynamic configuration of processing lanes, where each lane can be programmatically configured to execute different instruction sets and operational modes. This dynamic adaptability allows the system to optimize for specific workloads (scientific computing, data processing, AI inference) to achieve exascale performance while maintaining compatibility with multiple instruction set architectures through software-controlled lane configuration.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10445451B2Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features

Publication Date: 2019.10.15 INTEL CORP

AI summary

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. At least one of the plurality of processing elements includes a plurality of control inputs.