Configurable Spatial Accelerator With Dataflow Execution and Memory Prefetch
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Solution Overview
Problem
Exascale computing requires significant system-level floating point performance within a tight power budget, and classical von Neumann architectures struggle to simultaneously improve performance and energy efficiency due to high energy costs associated with out-of-order scheduling and complex register files.
Innovation Solution
A configurable spatial accelerator (CSA) is introduced, comprising an array of low-complexity, energy-efficient processing elements connected by lightweight, back-pressured networks, which directly execute dataflow graphs rather than transforming them into sequential instruction streams, allowing for parallel execution and efficient memory management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If classical von Neumann architectures are used to achieve high floating point performance, then system-level performance can be improved, but energy consumption increases significantly due to out-of-order scheduling and complex register files
Solution Approach 1:
The processor is segmented into multiple processing lanes (e.g., 16 lanes) that can execute instructions in parallel. Each lane has simplified execution units and shares common resources like register files and memory interfaces, reducing per-lane energy overhead while maintaining high aggregate floating point throughput
Solution Approach 2:
The processor implements a unified execution architecture where the same physical resources (register files, execution units, memory interfaces) serve multiple processing lanes simultaneously. This multi-functional design eliminates redundant components and reduces overall energy consumption while maintaining high performance
2Productivity
If out-of-order scheduling is implemented to improve performance, then instruction throughput increases, but device complexity and energy consumption increase
Solution Approach 1:
The out-of-order execution logic is segmented and distributed across processing lanes rather than centralized. Each lane maintains local instruction queues and execution state, reducing the complexity of global scheduling while enabling parallel out-of-order execution across lanes
Solution Approach 2:
The processor implements partial out-of-order execution where only critical paths and performance-sensitive instruction streams receive full out-of-order treatment, while less critical operations use simpler in-order execution, balancing throughput gains against complexity costs
3Adaptability or versatility
If complex register files are used to support multiple processing lanes, then register availability improves, but energy consumption and device complexity increase
Solution Approach 1:
Multiple processing lanes share common register files and execution resources through time-multiplexed access. The register files are designed with multiple ports and associativity to support concurrent access patterns, reducing total register storage requirements and energy consumption compared to dedicated registers per lane
Solution Approach 2:
The register file architecture is designed as a universal resource that serves all processing lanes through coordinated access control. The same physical register structures support multiple lanes' data storage and manipulation needs, eliminating redundant register files and reducing overall energy consumption
Data Source
AI summary
Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The processor also includes a streamer element to prefetch the incoming operand set from two or more levels of a memory system.