Spatial Accelerator Runtime Translation for Idle Resource Utilization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern spatial accelerators often sit idle due to the need for specialized compilers and software, limiting their utilization in heterogeneous CPUs, leading to inefficiencies in compute and memory resources.
Innovation Solution
A hardware controller that builds and maintains a dataflow graph-based architecture model to map instructions from CPUs to spatial accelerators, optimizing instruction latency and reconfiguring the accelerator using runtime performance data, enabling efficient execution of code regions and repurposing idle resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If spatial accelerators use specialized compilers and software stacks, then execution efficiency is improved, but device complexity and ease of operation deteriorate
Solution Approach 1:
The patent introduces a compilerless runtime system as an intermediary layer between the CPU and spatial accelerator. This runtime automatically translates high-level code regions into spatial accelerator instructions without requiring specialized compilers, thereby maintaining execution efficiency while eliminating the need for complex software stacks.
Solution Approach 2:
The spatial accelerator is designed to execute a universal instruction set that can handle multiple application domains without requiring domain-specific programming languages or compilers. This multi-functionality approach allows the same hardware architecture to serve general-purpose computing tasks while maintaining high efficiency.
2Productivity
If spatial accelerators require specialized programming, then domain-specialized execution is achieved, but ease of operation deteriorates
Solution Approach 1:
The compilerless runtime system performs automatic code analysis and transformation, enabling the spatial accelerator to execute domain-specialized workloads without manual intervention. The system automatically identifies suitable code regions, translates them into optimized spatial instructions, and manages resource allocation, making the accelerator easy to operate for all applications.
Solution Approach 2:
The runtime system acts as a mediator that translates high-level application code into domain-specific spatial accelerator instructions automatically. This eliminates the need for developers to learn specialized programming languages while still achieving domain-specialized execution through automatic code transformation.
3Ease of operation
If spatial accelerators are not explicitly programmed, then ease of operation is improved, but productivity deteriorates due to idle resources
Solution Approach 1:
The spatial accelerator system automatically identifies and executes suitable code regions without explicit programming by the user. The compilerless runtime monitors CPU execution, detects candidate code regions, and automatically offloads them to the spatial accelerator, ensuring high resource utilization while maintaining ease of operation.
Solution Approach 2:
The system implements feedback mechanisms where the runtime continuously monitors CPU execution performance and accelerator resource availability. Based on this feedback, it dynamically selects code regions for acceleration and adjusts resource allocation, thereby maximizing productivity without requiring explicit programming.
4Speed
If hardware mapping of instructions to planar grid is implemented, then translation speed is improved, but device complexity increases
Solution Approach 1:
The system performs preliminary analysis and organization of instructions into code regions before translation. By pre-identifying suitable code regions and organizing their instructions, the hardware mapping mechanism can operate more efficiently on structured data, improving translation speed while managing complexity through systematic preprocessing.
Data Source
AI summary
A method for translation and optimization for acceleration and its circuit are disclosed. The method includes: detecting a code region executing on a central processing unit (CPU) core for acceleration, the code region comprising a plurality of instructions; mapping, in hardware, the plurality of instructions in linear order to a planar grid for a spatial accelerator; configuring the spatial accelerator based on the planar grid; and transferring control to the spatial accelerator to execute the code region. Other aspects, embodiments, and features are also claimed and described.