Spatial-Array Processor Architecture for RISC-Like Programming
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Solution Overview
Problem
Existing reconfigurable and dataflow computing architectures are difficult to program sequentially, limiting their widespread adoption for complex software applications due to the need for specialized programming and lack of software transparency.
Innovation Solution
A processor architecture and instruction set that facilitates RISC-like programming by distributing instructions to a spatial array of processing elements, allowing simple fetching and decoding, with dataflow and control flow coordination through target instruction pointers, and enabling dynamic tiling for efficient execution of fragments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If reconfigurable and dataflow computing architectures are used, then energy efficiency is improved, but programming complexity increases and software transparency is lost
Solution Approach 1:
The processor is segmented into multiple processing elements (PEs) arranged in a spatial array, where each PE can independently execute instructions. This segmentation enables the system to maintain reconfigurability and energy efficiency while presenting a simplified programming interface, as the compiler can distribute instructions across multiple PEs without the programmer needing to understand the underlying complexity.
Solution Approach 2:
A compiler acts as an intermediary between the high-level programming language and the reconfigurable architecture. The compiler translates standard programming languages into instructions that can be executed on the spatial array of PEs, thereby hiding the programming complexity from the user while maintaining energy efficiency through the reconfigurable architecture.
2Productivity
If instructions are distributed to a spatial array of processing elements, then instruction reuse is increased, but fetch and decode operations increase
Solution Approach 1:
Instructions are pre-fetched and stored in local buffers within the spatial array of PEs before execution is needed. This preliminary action allows the processing elements to access instructions locally without repeated fetch operations from the main instruction stream, thereby increasing instruction reuse while reducing the time loss associated with fetch and decode operations.
3Productivity
If dynamic tiling is implemented for fragment execution, then execution efficiency is improved, but architectural complexity increases
Solution Approach 1:
The processor implements dynamic tiling, where the spatial array of PEs can be reconfigured into different tile structures during runtime based on the execution requirements of different code fragments. This dynamic reconfiguration allows the system to optimize execution efficiency for different workloads while managing architectural complexity through automated reconfiguration mechanisms.
Data Source
AI summary
A processing element array of a processor, comprising a plurality of processing elements or nodes, each of the processing elements including at least one instruction register, a control unit, at least one arithmetic or logic unit, and one or more storage elements, and being configured to store, decode and execute an instruction; the instruction register and the storage elements are configured to be writable from one or more data buses; and the arithmetic or logic unit is configured to receive input from one of the storage elements and to output a result to one or more other processing elements of the array of processing elements via the one or more data buses. Also, a fabric cell or tile of a processor, comprising such a processing element array, an S bus that constitutes the data bus, and a cell or tile interface node. The interface node connects an external message bus to the S bus of the fabric cell; the S bus implements the datapath of the processing elements, and facilitates data exchange between the processing elements, and between the interface node and the cell or tile interface node and processing elements; and the interface node comprises a plurality of message registers and is configured to forward instructions to the processing elements, coordinate eviction and restoring locally, and assist the processing elements during the execution of communication and fragment instance management instructions.