Spatially Aware DFT for Integrated Circuit Testing

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Solution Overview

Problem

Existing integrated circuit testing methods lack efficiency in ensuring functional correctness and reliability due to simultaneous toggling of high-speed circuits, which can lead to inaccurate yield assessment and increased test time.

Innovation Solution

The implementation of spatially aware Design for Testability (DFT) techniques, which involve applying DFT test patterns such as ATPG, LBIST, MBIST, and EDT to targeted portions of the circuit under test, using preconfigured policies for dividing the physical layout, associating clock signals, and implementing data path gating to avoid simultaneous toggling of high-speed circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If simultaneous toggling of high-speed circuits is used during testing, then test coverage is improved, but power consumption increases and test accuracy decreases

Engineering Contradiction:

Improvetest accuracyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The circuit under test is divided into multiple spatial zones based on physical location and switching activity characteristics. Each zone is independently controlled with its own test pattern application, allowing selective activation of circuit portions to reduce simultaneous toggling while maintaining comprehensive test coverage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different test strategies are applied to different spatial zones based on their specific characteristics. High-switching-activity regions receive targeted test patterns while low-activity regions are monitored or tested with reduced intensity, optimizing the balance between test thoroughness and power consumption.

Inventive Principle:

Principle #3Local quality

2Measurement precision

If comprehensive testing of entire circuit is performed, then yield assessment accuracy is improved, but test time increases

Engineering Contradiction:

Improveyield assessment accuracyVSAvoidtest time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The circuit is partitioned into spatial zones that can be tested in parallel or sequentially. This segmentation allows comprehensive testing of the entire circuit to be distributed across multiple independent test operations, reducing overall test time while maintaining complete coverage for accurate yield assessment.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Testing is performed in periodic cycles across different spatial zones rather than simultaneously across the entire circuit. Each zone undergoes comprehensive testing during its designated time window, enabling complete circuit validation without requiring all regions to be tested at once, thus reducing total test time.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS20250148182A1Spatially aware low power techniques for design for testability

Publication Date: 2025.05.08 MICRON TECHNOLOGY INC

AI summary

The subject application relates to spatially aware Design for Testability (DFT). For instance, a method may include dividing a layout of a circuit under test (CUT) into a plurality of grids based on a preconfigured policy, creating, based on the preconfigured policy, a plurality of targeted portions from the divided layout of the CUT, applying a DFT test pattern to the plurality of targeted portions; and capturing data output from the plurality of targeted portions.