Spatially Resolved Netlists for Post-Silicon Change Detection
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Solution Overview
Problem
The lack of visibility into the supply chain for chip fabrication introduces vulnerabilities, and existing methods for post-silicon verification and validation struggle with differentiating errors from malicious changes due to fabrication processes, especially as node sizes shrink, necessitating a methodology that integrates both behavioral and spatial comparisons.
Innovation Solution
A spatially resolved netlist that combines logical and physical characteristics of a circuit design, providing a graphical representation that includes physical location information and cell/net definitions, enabling more accurate verification and validation by integrating spatial and logical information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If image processing and polygon extraction processes are used to produce transistor level layout, then layout recovery is achieved, but manufacturing precision deteriorates due to optical proximity corrections and artifacts from sample preparation
Solution Approach 1:
The verification process is segmented into multiple independent comparison dimensions: behavioral comparison (logical functionality) and spatial comparison (physical layout). This allows differentiation between errors and intentional changes by analyzing each dimension separately, with spatial comparison addressing the manufacturing precision issues through localized analysis of specific layout regions.
Solution Approach 2:
A spatially resolved netlist is introduced as an intermediary data structure that bridges the gap between behavioral netlists (logical) and physical layouts (geometric). This intermediary layer incorporates both connectivity information and spatial location data, enabling accurate comparison that accounts for fabrication artifacts while maintaining verification precision.
2Ease of operation
If behavioral comparison alone is used for verification, then verification process is simple, but measurement precision deteriorates as it cannot differentiate errors from true changes
Solution Approach 1:
The verification methodology merges behavioral comparison (logical connectivity) and spatial comparison (physical geometry) into a unified verification framework. The spatially resolved netlist combines both logical and physical characteristics, allowing the system to distinguish between fabrication errors and intentional design changes by analyzing both dimensions simultaneously.
Solution Approach 2:
The verification approach transitions from one-dimensional behavioral comparison to two-dimensional verification by adding spatial dimension. This dimensional expansion enables the system to detect changes in both logic and physical layout, improving measurement precision while maintaining operational simplicity through automated multi-dimensional comparison.
3Quantity of substance
If node sizes shrink, then device density improves, but manufacturing precision deteriorates due to increased sensitivity to fabrication variations
Solution Approach 1:
The verification system applies local quality analysis by examining specific spatial regions and features at different levels of detail. The spatially resolved netlist enables localized comparison of critical features, allowing the system to identify and accommodate fabrication variations in specific areas while maintaining overall verification accuracy despite shrinking node sizes.
Data Source
AI summary
The present disclosure provides a method for generating a spatially resolved netlist that includes generating a netlist based on integrated circuit (IC) layout data and standard cell library data, the netlist including cell and net definitions associated with the IC; determining position data for respective cells and nets based on the IC layout data; mapping the position data to respective cell and net definitions in the netlist; and generating a spatially resolved netlist that includes the mapped position data to respective cell and net definitions.