Spatially Programmed Logic Array Architecture for Dynamic Resource Allocation
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Solution Overview
Problem
The existing cloud computing technologies face challenges in dynamically reallocating programs intended for spatially-programmed logic circuits (SPLCs) like field programmable gate arrays (FPGAs) due to the complexity and time-consuming nature of spatial compilation, making it impractical for real-time, flexible resource allocation.
Innovation Solution
The solution involves pre-compiling SPLC programs into predefined virtual blocks that can be mapped flexibly to different SPLC hardware blocks through a simple offsetting process, allowing for relocation without recompilation, and providing mechanisms for inter- and intra-SPLC communication to facilitate scalable and efficient resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If spatial compilation is used to map programs to specific FPGA hardware locations, then program execution efficiency is improved, but the time required to recompile and reallocate programs becomes excessively long
Solution Approach 1:
The patent pre-organizes FPGA resources into standardized virtual blocks during system initialization, creating a mapping framework before programs need to be allocated. This preliminary structuring allows programs to be compiled once to virtual block addresses, and then quickly mapped to physical hardware without time-consuming recompilation when reallocation is needed.
Solution Approach 2:
The patent introduces virtual blocks as an intermediary layer between program code and physical FPGA hardware. Programs are compiled to virtual block addresses rather than direct hardware addresses, and a mapping mechanism translates virtual addresses to physical locations. This intermediary abstraction enables fast reallocation by changing only the mapping, not the program itself.
2Speed
If programs are compiled to specific physical FPGA locations for optimal performance, then execution speed is improved, but flexibility to relocate programs dynamically is lost
Solution Approach 1:
The patent segments the FPGA hardware into multiple identical or heterogeneous virtual blocks, each capable of executing program functions. Programs are compiled to run on virtual blocks rather than specific physical locations. This segmentation allows the same program to be distributed across different physical blocks or relocated between FPGAs without recompilation, maintaining both speed and flexibility.
Solution Approach 2:
The patent creates universal virtual blocks that can execute any program function through configuration, rather than hardcoding functions to specific physical locations. Each virtual block is designed to be multi-functional, capable of being programmed to perform different operations. This universality allows programs to be flexibly allocated and relocated while maintaining execution efficiency.
3Productivity
If FPGAs are pre-programmed with specific accelerator functions, then performance for those functions is improved, but the ability to dynamically allocate resources for different programs is reduced
Solution Approach 1:
The patent implements dynamic resource allocation by allowing virtual blocks to be configured at runtime based on program requirements. Instead of static pre-programming, the system dynamically assigns virtual blocks to programs and configures their functionality through loading appropriate bitstreams or configuration data. This dynamic approach maintains high performance for accelerator functions while enabling flexible reallocation for different programs.
Data Source
AI summary
A spatially programmed logic circuit (SPLC) array system performs spatial compilation of programs for use in the SPLCs to produce standardized compiled blocks representing predetermined portions of an SPLC. The blocks may be freely relocated in an SPLC after compilation by editing of the compiled file. Inter-block communication circuitry allows joining of blocks within an SPLC or across SPLCs to allow scalability and accommodation of different programs with efficient utilization of an SPLC for multiple programs, again without recompilation.