SPC Concatenated Decoder Using Parity-Bit Likelihood Updates
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Solution Overview
Problem
Current high data rate coded transmission concepts, such as turbo codes, face challenges with high decoding complexity and suboptimal performance at very high coding rates, particularly in applications like HSDPA with transmission rates above 10 Mbps, and require more efficient channel coding schemes.
Innovation Solution
The development of parallel concatenated single-parity-check (SPC)-based zigzag codes and low complexity accumulated convolutional codes, which significantly reduce decoding complexity and offer performance comparable to turbo codes, with properly constructed zigzag codes outperforming turbo codes at high coding rates and low complexity constructions matching turbo code performance at medium coding rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If turbo codes are used for high data rate transmission, then error correction performance is improved, but decoding complexity increases significantly
Solution Approach 1:
The patent segments the complex turbo code decoding problem into simpler component decoding tasks. By using parallel concatenated SPC codes with independent parity check equations, the decoding process is divided into multiple simple parity check operations that can be performed in parallel, reducing overall decoding complexity while maintaining error correction performance.
Solution Approach 2:
The patent changes the code structure parameters from traditional turbo codes to SPC-based concatenated codes. This parameter change involves using single-parity-check codes with specific rate configurations (e.g., rate 1/2, 2/3, 3/4) and parallel concatenation structures, which fundamentally alters the decoding complexity characteristics while preserving reliability.
2Reliability
If traditional turbo codes are used, then performance approaches Shannon capacity, but decoding complexity remains too great for practical applications
Solution Approach 1:
The patent employs simple SPC code structures that are computationally inexpensive to decode. Each SPC component code requires only simple parity check operations rather than complex APP decoding, making the overall system more practical for real-time applications while still achieving performance close to Shannon capacity through parallel concatenation.
Solution Approach 2:
By segmenting the coding scheme into parallel SPC component codes, the patent enables independent and simple decoding operations for each component. This segmentation transforms the intractable decoding problem of traditional turbo codes into a series of manageable parity check operations that are practical for implementation.
3Device complexity
If SPC-based codes are used to reduce complexity, then decoding complexity decreases, but performance at medium coding rates may be suboptimal
Solution Approach 1:
The patent creates a composite coding structure by parallel concatenating multiple SPC codes with different rates and characteristics. This composite structure combines the advantages of different SPC variants, achieving both low decoding complexity and improved performance at medium coding rates through the synergistic effect of the concatenated components.
Solution Approach 2:
The parallel concatenated SPC structure provides multi-functionality by accommodating different coding rates and performance requirements through configuration of the component SPC codes. The same basic structure can be adapted for various coding rates (1/2, 2/3, 3/4, etc.), making it universally applicable across different medium coding rate scenarios while maintaining both simplicity and performance.
Data Source
AI summary
This invention provides an iterative PCZZ data decoder that includes circuitry for utilizing all extrinsic information during iterative decoding by updating likelihood information for parity bits LPi, i=1, . . . , M during iterations. The extrinsic information for the parity bits is included in iterations by re-calculating soft values for parity bits LPi(k) for each iteration k. In one embodiment the parity bit soft values are re-calculated in a plurality of circuit blocks following Max-Log-APP (MLA) decoder blocks, based on soft values for data bits LDi(k). In another embodiment the parity bit soft values are re-calculated recursively within the plurality of MLA decoders. The decoder operates to control the convergence of the decoder by monitoring a soft value of one parity check symbol, e.g., L(k−1)[p(IM)], where p(IM) represents the last parity check bit in an I×M parity check array. A decoder iteration stopping rule may be implemented by testing a likelihood measure associated with a last parity check symbol in a parity check column. In one case the likelihood measure may be given by L(k−1)[p(IM]>threshold, and in another case the likelihood measure may be given by L(k−1)[p(I)]>threshold. The likelihood measure is given in general by: L(k−1)[p(I)]>threshold, L(k−1)[p(2I)]>threshold, . . . , L(k−1)[p(IM)]>threshold, where the value of the threshold is a function of data block size.