Set-Partitioned Coded Modulation for DOCSIS Channel Capacity

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Solution Overview

Problem

Conventional point-to-multipoint communication systems, such as cable modem systems, face challenges in maintaining channel capacity due to increased demand for bandwidth, particularly in downstream transmissions, which are not adequately addressed by existing DOCSIS specifications like DOCSIS 2.0, leading to deficiencies in supporting high-demand services like HDTV and digital services.

Innovation Solution

The implementation of set-partitioned coded modulation (SPCM) with inner and outer coding, utilizing forward error correction codes like LDPC and Reed-Solomon codes, to enhance error correction and adapt to varying channel conditions, thereby increasing channel capacity and mitigating burst noise and AWGN.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional DOCSIS 2.0 specifications are used for downstream transmissions, then existing system compatibility is maintained, but channel capacity is insufficient to support increased bandwidth demand for services like HDTV and digital services

Engineering Contradiction:
Improvechannel capacityVSAvoidsupport for high-demand services
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent applies parameter changes by transitioning from conventional DOCSIS 2.0 modulation and coding parameters to advanced parameters including set-partitioned coded modulation (SPCM) with inner and outer coding, LDPC codes, and Reed-Solomon codes. This enables the system to achieve higher spectral efficiency and support increased bandwidth demand while maintaining backward compatibility through gradual deployment strategies

Inventive Principle:
Principle #35Parameter changes

2Reliability

If forward error correction codes like LDPC and Reed-Solomon codes are implemented, then error correction capability and channel capacity are enhanced, but system complexity and implementation difficulty increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidsystem implementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the error correction function into two distinct layers: inner coding using LDPC codes for correcting random errors, and outer coding using Reed-Solomon codes for correcting burst errors. This segmentation allows each coding layer to be optimized independently and simplifies the overall system design by dividing the complex error correction task into manageable, specialized components

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary decoding architecture that processes inner and outer coded signals through separate but coordinated decoding paths. This intermediary structure enables the system to handle different error types through specialized decoders before combining results, reducing the complexity burden on any single decoder while maintaining high reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If set-partitioned coded modulation with inner and outer coding is used, then robustness against burst noise and AWGN is improved, but transmission latency and memory requirements increase

Engineering Contradiction:
Improverobustness against burst noise and AWGNVSAvoidtransmission latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing optimal decoding sequences and lookup tables for both inner and outer codes during system initialization. This preliminary preparation enables the decoders to operate with reduced real-time computation requirements, minimizing additional latency introduced by the enhanced error correction mechanisms while maintaining robustness against burst noise and AWGN

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9042492B2Staggered transmission and reception for reducing latency and memory
Publication Date: 2015.05.26 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9042492B2 patent drawing
  • US9042492B2 patent drawing
  • US9042492B2 patent drawing

AI summary

A demodulator processes a continuous-time signal to generate at a plurality of encoded bits. An inner decoder processes a first subset of bits within the plurality of encoded bits to correct selected ones of the first subset of bits to form a corrected first subset of bits and to generate partially corrected data from the plurality of encoded bits based on the corrected first subset of bits. An outer decoder processes the partially decoded data, to correct selected ones of a second subset of the plurality of encoded bits to form a corrected second subset of bits. A bit combiner generates data estimates by combining the corrected first subset of bits and the corrected second subset of bits.