SPDIF Clock Data Recovery Using Toothless Digital Rate Generator
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data recovery systems rely on Phase-Locked Loops (PLL) to synchronize with incoming data streams, which are prone to jitter and other failure mechanisms, and are not effective for irregular or bursty data streams without generating a frequency-locked clock.
Innovation Solution
A data recovery system that acquires data without synchronization to the input data stream frequency, using a digital oversampler, sample receiver, multiplexer, sample rate converter, and rate generator to produce a 'toothless' clock signal that matches the data stream's sample rate, eliminating the need for PLL and reducing power and expense while handling various data stream types, including SPDIF, USB, and clock-less sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a Phase-Locked Loop (PLL) is used to synchronize data sampling with the incoming data stream, then data recovery accuracy is improved, but the system becomes prone to jitter and other failure mechanisms
Solution Approach 1:
The patent extracts the synchronization function from the traditional PLL-based sampling clock and implements it separately in the digital domain using a buffer and read pointer mechanism. This separates the analog clock generation (which causes jitter) from the digital data recovery process, eliminating jitter while maintaining synchronization accuracy.
Solution Approach 2:
The patent replaces the mechanical/analog PLL system with a digital buffer-based synchronization mechanism. Instead of using analog phase and frequency locking, the system uses digital buffering and pointer tracking to achieve synchronization, thereby eliminating analog jitter and improving reliability.
2Measurement precision
If a PLL is used to generate a clock matching the input data stream frequency, then synchronous sampling is achieved, but power consumption and system complexity increase
Solution Approach 1:
The patent replaces the power-hungry analog PLL circuitry with a digital buffer and simple pointer arithmetic operations. This substitution dramatically reduces power consumption while maintaining the ability to synchronize sampling with the input data stream frequency.
3Productivity
If a PLL is used for data stream synchronization, then regular data streams are handled effectively, but irregular or bursty data streams cause PLL failure
Solution Approach 1:
The patent implements a dynamic buffer management system where the read pointer adjusts its position based on the actual arrival rate of data packets. This dynamic adjustment allows the system to handle variable-rate and bursty data streams effectively, unlike fixed-frequency PLLs that fail with irregular inputs.
Solution Approach 2:
The buffer-based synchronization mechanism serves multiple functions: it handles regular continuous streams, irregular streams, and bursty streams uniformly. This universal approach replaces the specialized PLL design that only works well with regular periodic inputs.
4Speed
If conventional sample rate converters using analog PLLs are used, then clock-locked output is achieved, but jitter and expense increase
Solution Approach 1:
The patent replaces analog PLL-based sample rate conversion with a digital implementation using buffers and read pointers. This eliminates analog jitter while maintaining precise clock synchronization and sample rate conversion capability, reducing both jitter and expense.
Data Source
AI summary
A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.