S/PDIF Decoder Using Pulse Width Oversampling
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Solution Overview
Problem
Existing methods for decoding bi-phase mark coded S/PDIF signals face challenges in clock recovery, particularly with analog PLLs being difficult to integrate with digital logic and prone to synchronization drift, while digital solutions can be cumbersome and costly to implement effectively.
Innovation Solution
A method and system for decoding S/PDIF signals that oversamples pulse widths using a high-frequency clock to acquire synchronization without relying on phase locked loops, using a sync and reference value acquisition digital logic to measure and store reference pulse widths, allowing for accurate decoding and automatic re-synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog PLLs are used for clock recovery, then clock synchronization can be achieved, but integration with digital logic is difficult and synchronization drift occurs
Solution Approach 1:
The patent replaces the analog PLL mechanism with a digital-based clock recovery system that uses pulse width measurement and counter circuits. The digital logic measures pulse widths of the bi-phase mark coded signal and generates a recovered clock signal through digital counting and timing operations, eliminating the need for analog components and their associated integration challenges.
2Reliability
If analog PLLs are used for clock recovery, then clock synchronization can be achieved, but clock drift occurs requiring extra monitoring circuitry
Solution Approach 1:
The digital measurement-based clock recovery inherently provides stable timing reference without drift. By measuring pulse widths directly and using digital counters synchronized to the data stream, the system maintains accurate timing without the drift problems of analog PLLs, eliminating the need for additional monitoring and re-synchronization circuitry.
3Ease of manufacture
If digital solutions are used for clock recovery, then integration with digital logic is improved, but implementation becomes cumbersome and costly
Solution Approach 1:
The patent divides the clock recovery function into discrete digital modules: pulse width measurement circuits, counter circuits, and timing control logic. Each module performs a specific function and can be independently implemented using standard digital logic components, making the overall system easier to manufacture and integrate into ASICs or FPGAs.
Solution Approach 2:
The digital measurement system uses the data stream itself to generate the timing reference. By measuring pulse widths of incoming data transitions and using these measurements to drive the recovered clock, the system is self-synchronized and does not require external calibration or complex control algorithms, reducing implementation complexity.
Data Source
AI summary
A system and method for decoding coded data streams is disclosed. In one embodiment, in a method for decoding coded data streams, a coded data stream including an embedded input clock signal is oversampled to measure substantially sequentially a plurality of pulse widths in a current frame using a sync and reference value acquisition digital logic. The coded data steam includes a plurality of frames, and each frame includes a preamble of fixed length and a series of data bits. The oversampling is performed using a high frequency clock signal having a substantially higher frequency than a frequency of the embedded input clock signal. Then, the coded data stream is decoded based on the measured plurality of pulse widths in the current frame using a data decoder.