Frequency Determining Circuit for Stable SPDIF Lock Detection
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Solution Overview
Problem
Conventional frequency determination methods for SPDIF signals struggle with maintaining a locked state due to signal interference and clock frequency inconsistencies, leading to data loss and prolonged unlocked states.
Innovation Solution
A signal receiving device and frequency determining circuit that utilize a counter and comparators to compare bit counts with preset values, adjusting the type indicator based on previous values to sustain a locked state and reduce data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional two-part frequency determination method is used to compare bit count with a reference value, then frequency determination can be made, but the system frequently enters unlocked state due to signal interference and clock frequency inconsistencies causing fluctuations around the 46K base frequency
Solution Approach 1:
The patent applies dynamics by making the frequency determination system adaptive rather than static. The type indicator is dynamically updated based on continuous comparison of bit counts with reference values, allowing the system to adapt to frequency fluctuations caused by signal interference and clock inconsistencies. This dynamic adjustment prevents the system from remaining in an unlocked state and reduces data loss during frequency transitions.
Solution Approach 2:
The patent implements feedback by continuously monitoring bit counts and comparing them with reference values to update the type indicator. This closed-loop feedback mechanism allows the system to detect frequency deviations and correct them by updating the type indicator accordingly, thereby maintaining a stable locked state despite external interference and clock frequency variations.
2Productivity
If the type indicator is updated based on bit count comparison with a single reference value, then frequency classification can be achieved, but data loss occurs during frequency changing state transitions
Solution Approach 1:
The patent applies preliminary action by preparing the type indicator updates in advance based on bit count comparisons. The system continuously monitors and prepares frequency determination results before actual frequency transitions occur, allowing smooth state changes that prevent data loss during transitions between different base frequency types.
3Device complexity
If a single reference value is used for frequency determination, then the determination process is simple, but the system cannot tolerate frequency fluctuations around the base frequency
Solution Approach 1:
The patent applies parameter changes by using multiple reference values corresponding to different base frequency types (44.1K and 48K families). Instead of relying on a single reference value, the system compares bit counts against multiple references and selects the appropriate type indicator, thereby expanding the tolerance range for frequency fluctuations while maintaining reasonable circuit complexity through systematic comparison logic.
Data Source
AI summary
A signal receiving device is adapted for receiving a multi-bit signal-under-test that supports one of first and second base frequency types, and outputting a type indicator for indicating which one of the first and second base frequency types is supported by the signal-under-test. The signal receiving device includes a counter and a frequency determining circuit. The counter includes an accumulating unit for counting cycles of an operating clock so as to obtain a bit count. The frequency determining circuit is coupled to the counter for comparing the bit count to one of first and second preset values in accordance with a previous value of the type indicator so as to obtain a comparison result, and determining whether to update a value of the type indicator based on the comparison result.