SPDT Switch Biasing Layout for High Linearity and Low Return Loss
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Solution Overview
Problem
Existing SPDT switches face limitations in linearity due to insufficient bootstrapping and return loss degradation caused by parasitic capacitance associated with on-chip coupling capacitors, which affects the performance of radio frequency and millimeter-wave signal routing.
Innovation Solution
The design incorporates auxiliary transistors and coupling capacitors to maintain consistent bias voltages across switching transistors, eliminating the need for intervening coupling capacitors at the common terminal, thereby enhancing linearity and reducing parasitic capacitance effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coupling capacitors are used at the common terminal to maintain bias voltages, then the switching performance is improved, but parasitic capacitance increases causing return loss degradation
Solution Approach 1:
The patent removes the coupling capacitors from the common terminal of the SPDT switch, extracting the harmful parasitic capacitance element while maintaining the necessary biasing function through alternative means (direct connection of switching transistor drains to common terminal). This eliminates the source of return loss degradation while preserving switching performance.
Solution Approach 2:
The patent changes the biasing approach by using auxiliary transistors with controlled channel widths (at most 50% of main switching transistor channel width) to provide bootstrapping without requiring coupling capacitors. This parameter change in the biasing mechanism achieves the necessary voltage maintenance without introducing parasitic capacitance.
2Manufacturing precision
If bootstrapping is increased to improve linearity, then signal routing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies bootstrapping locally only where needed - using auxiliary transistors connected to the gates of the main switching transistors to maintain proper bias voltages. This localized approach improves linearity at the critical switching nodes without requiring complex global bootstrapping circuits, thereby avoiding excessive device complexity.
Solution Approach 2:
The patent controls the bootstrapping effect by limiting the auxiliary transistor channel widths to at most 50% of the main switching transistor channel widths. This parameter control provides sufficient bootstrapping for high linearity while preventing excessive complexity in the biasing network.
Data Source
AI summary
A single-pole double-throw switch. In some embodiments, the switch includes a first switching transistor connected between a common terminal of the single-pole double-throw switch and a first switched terminal of the single-pole double-throw switch, a second switching transistor connected between the common terminal of the single-pole double-throw switch and a second switched terminal of the single-pole double-throw switch, a first auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the first switching transistor, and a second auxiliary transistor connected between the common terminal of the single-pole double-throw switch and a gate of the second switching transistor.