SPDT Switch Gate Control for Power Transition Delay
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Solution Overview
Problem
In mobile communication systems, the introduction of Dual Transfer Mode (DTM) in GSM systems, where both voice and data communication occur within the same frame, leads to varying high frequency power levels, causing a rise delay and increased harmonic distortion due to the transition from high power (33 dBm) to low power (5 dBm) time slots, resulting in transmission power loss.
Innovation Solution
A semiconductor integrated device with a booster circuit and voltage controller is used to manage the switching transistor's operation, generating a boosted voltage and controlling the drain voltage to prevent charge accumulation and ensure the drain voltage remains lower than the gate voltage, thereby preventing output power rise delays and reducing harmonic distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a booster circuit is used to reduce harmonic distortion by applying a negative voltage to the gate of the OFF-state FET, then the harmonic distortion is reduced, but when the transmission power transitions from high to low, the drain voltage remains higher than the gate voltage causing a rise delay in output power
Solution Approach 1:
A voltage controller circuit is introduced as an intermediary between the booster circuit and the FET gate. This mediator monitors the voltages at the gate and drain, and selectively connects the gate to either the boosted voltage or a reference potential based on the comparison result, thereby resolving the conflict between harmonic distortion reduction and power rise speed
Solution Approach 2:
The voltage controller implements a feedback mechanism by continuously monitoring the gate voltage and drain voltage, comparing them, and adjusting the gate connection state accordingly. This feedback loop ensures that the gate voltage always remains lower than the drain voltage during power transitions, preventing rise delays while maintaining low harmonic distortion during steady state
2Object-generated harmful factors
If the gate voltage is kept low to reduce capacitance and harmonic distortion, then the FET remains in a deep OFF state reducing distortion, but the output power cannot rise quickly when transitioning from high to low power modes
Solution Approach 1:
The gate voltage is made dynamic rather than static. The voltage controller adjusts the gate connection state in real-time based on the power transition state. During high-to-low power transitions, the gate is temporarily connected to the reference potential to enable fast rise, while during steady low-power operation, the gate remains connected to the boosted voltage to maintain low harmonic distortion
Solution Approach 2:
The voltage controller detects the power transition state in advance and proactively adjusts the gate voltage before the output power rise delay occurs. By monitoring the transmission power level changes, the controller prepares the FET gate in advance to ensure rapid power transition when needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents output power rise delays and improves harmonic distortion characteristics, enhancing the reliability of communication equipment by maintaining the drain voltage below the gate voltage, even during transitions between high and low power time slots.
Implementation Method 1
a booster circuit for taking a transmission signal output through the switching transistor when a signal is input through the fourth terminal, generating a boosted voltage higher than the voltage level of the input signal, and applying the boosted voltage to a control terminal of the switching transistor
Implementation Method 2
a voltage controller for performing control so that when the signal level of the transmission signal output through the switching transistor decreases, a drain voltage of the switching transistor is not higher than a gate voltage of the switching transistor
Data Source
AI summary
Switching characteristics in an SPDT switch are improved to reduce the rise delay in a low power slot following after a high power slot. Control terminals of an SPDT switch are respectively provided with backflow prevention circuits. The backflow prevention circuit is configured to have two transistors and a diode. In a transmission mode, for example, when a time slot where a high power passes through transistors is followed by a time slot where a low power passes through, the electric charges accumulated in the gates of the transistors are blocked. In the case where the transistors are in the OFF state, the electric charges accumulated in the gates of the transistors are immediately discharged to allow the transistors to be completely turned OFF.