Synchronous Payload Envelope Mapping Without Pointer Adjustments
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Solution Overview
Problem
In synchronous communications networks, the need for pointer adjustments to account for clock and phase variations leads to jitter and wander issues, causing data rate inconsistencies and potential data loss due to overflow or underflow conditions in elastic stores, especially when dealing with different clock frequencies across the network.
Innovation Solution
A method and system that generate Synchronous Payload Envelopes (SPEs) with identically-positioned information bytes, eliminating the need for pointer adjustments by maintaining constant pointer values and adjusting the data rate based on buffer fill conditions, allowing for seamless transmission across different clock rates without frame re-synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pointer adjustments are used to account for clock and phase variations, then data rate inconsistencies are corrected, but jitter and wander issues occur causing data loss
Solution Approach 1:
The patent extracts the harmful pointer adjustment mechanism from the data path by using a separate timing recovery loop that operates independently. The phase detector and voltage controlled oscillator adjust the clock signal without requiring pointer modifications to the actual data stream, thereby eliminating jitter and wander while maintaining data integrity.
Solution Approach 2:
The patent introduces an intermediary timing recovery mechanism consisting of a phase detector and voltage controlled oscillator that mediates between the incoming signal and the data extraction process. This intermediary system corrects timing variations through clock signal adjustment rather than direct pointer manipulation, preventing the harmful effects of jitter and wander.
2Adaptability or versatility
If elastic stores are used to handle clock frequency differences, then data rate variations are accommodated, but overflow or underflow conditions cause data loss
Solution Approach 1:
The patent performs preliminary timing synchronization by using a phase detector to detect phase differences before data is written to or read from the elastic store. The voltage controlled oscillator preemptively adjusts the clock signal to minimize phase variations, preventing overflow and underflow conditions before they occur.
Solution Approach 2:
The patent implements a feedback mechanism where the phase detector continuously monitors the phase difference between the incoming signal and the local clock, and the voltage controlled oscillator adjusts the clock frequency in real-time based on this feedback. This closed-loop control maintains the elastic store at optimal fill levels, preventing data loss from overflow or underflow.
3Reliability
If frame re-synchronization is performed to maintain constant pointer values, then data rate consistency is improved, but transmission complexity increases
Solution Approach 1:
The patent replaces the mechanical frame re-synchronization process with an electronic timing recovery mechanism. Instead of physically repositioning or re-framing data to maintain constant pointers, the system uses a phase detector and voltage controlled oscillator to electronically adjust the clock signal, achieving the same effect with simpler operations.
Data Source
AI summary
A system and method are provided for mapping information into Synchronous Payload Envelopes (SPEs). The method provides information bytes at a nominal system clock-based data rate, which is about equal to a system clock, but may be adjusted. An external clock has a rate approximately equal to the system clock rate. The method generates SPEs with identically-positioned information bytes, regardless of differences between the system and external clock rates. The SPEs are combined with Transport Overhead (TOH) and transmitted as a message frame at the external clock rate. SPEs are generated maintaining the positions of the information bytes within each SPE, without pointer adjustments, despite differences between the system and external clock rates. Expressed another way, message frames are generated with payload and TOH sections, and the information bytes are located exclusively in the payload sections. As a result, constant pointer values (e.g., H1/H2 or V1/V2) are maintained for all the SPEs.